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These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

This paper proposes an LCCC and CCL compensated wireless servo motor control circuitry utilizing the merits of fundamental and third harmonic. With this circuitry, the motor side needs no additional power supply and controller, which significantly reduces the difficulty of maintenance. Besides, benefiting from the proposing of CCL compensating topology and utilizing of the self-driven circuitry, the secondary operates in fully resonant state and the motor direction control H-bridge is self-driven by the LC frequency selecting circuitry (FSC). Moreover, compared with the conventional motor control circuitry, because of the use of fundamental and third harmonic, the power equalization becomes significantly easier, and zero voltage switch (ZVS) can be realized at the same time; Besides, motion direction control of the motor is simpler with only a single pole double throw (SPDT) at the transmitter side. In addition, system resource consumption is reduced compared with conventional motor drive topologies. In this paper, an 180W prototype is built for experimental verification, and the result shows a good power equalization capability and a transfer efficiency reaching up to 90% at the distance of 10cm. [ABSTRACT FROM AUTHOR]

This paper is concerned with distributed consensus control of unknown multiagent systems. As the system’s dynamics is unknown, an adaptive Fourier decomposition (AFD) based iterative learning control (ILC) dynamics adaptive matching method in frequency domain is put forward to deal with it. First, large amounts of input and output measurement data are used to estimate the frequency domain characteristics of the system by Takenaka-Malmquist functions. Second, convert the traditional time domain ILC to the frequency domain to establish a matching relationship with the estimated frequency domain features. Then, an adaptive iterative learning rate is constructed to achieve the optimal convergence at each sampling point. The feasibility of the proposed algorithm is guaranteed by the convergence of AFD in Hardy space $H^{2}(\mathbb {D})$ under the maximum selection principle. Compared with the reinforcement learning data-driven control scheme, the method proposed in this paper has obvious advantages in the control accuracy and convergence efficiency. In addition, this paper takes two kinds of denoising algorithms based on unwinding AFD to deal with the multi-agent systems with channel noise. Finally, the feasibility and effectiveness of the developed method are verified by a series of simulations. [ABSTRACT FROM AUTHOR]

In this paper, a Takenaka-Malmquist (TM) basis function based equivalent data-model is established by an adaptive rational decomposition for the finite-time interval trajectory tracking control and real-time control of a class of nonlinear systems in the frequency domain. This data model can adaptively learn and match the control process of nonlinear systems. As a result, the proposed trajectory tracking as well as real-time control method can reflect the feature of adaptive learning in order-by-order decomposition, and the feasibility of the proposed method is guaranteed by the convergence of adaptive decomposition by TM basis function under the maximum selection principle (MSP) in Hardy space $H^{2}(\mathbb {D})$. Compared with the traditional model-free control method, this data learning model which matches the control process has obvious advantages in the system model expression and control accuracy. Simulation results at the end of this paper show the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

This paper provides a comprehensive study of signal integrity issues in RRAM-based neuromorphic chip crossbar arrays due to interconnect parasitic. First, the parasitic parameters of the crossbar array are calculated by the partial equivalent element circuit (PEEC) method with an efficient unit-cell approach. Numerical experiments show that for a $50\times 50$ array scale, this method consumes only 1.5% of the calculation time of the commercial software based 3D model, which translates to a calculation speed up of 72 times. Moreover, the PEEC circuit simulation results match well with those of the 3D model. Then, we investigate the effects of parasitic parameters such as capacitance and inductance, as well as the feature size of the crossbar array on signal integrity. All of them will lead to corresponding changes in parasitic effects, which in turn result in the most common signal integrity issues such as crosstalk, time delay and mutual capacitive coupling induced sneak path problem. Different from other studies, the excitation used in this paper is the neural spike signal generated by the Izhikevich neuron model, which is both rich in dynamic characteristics and high in computational efficiency. Finally, based on the study we propose a simple but effective design scheme for reduction of signal distortion, which can provide valuable design guidance for neuromorphic systems to achieve high performance and high computational accuracy. [ABSTRACT FROM AUTHOR]

In this paper, the adaptive fuzzy control of switched stochastic nonlinear systems with set-time prescribed performance based on event-driven mechanism is studied. The creative part of this paper is that based on the set-time performance function, a modified event-triggered strategy that considers asynchronous switching to deteriorate system performance without strict assumptions is presented, which avoids Zeno behavior and saves communication resources. Then, by using backstepping recursive design technique, It $\hat {o}$ ’s differential lemma and mode-dependent average dwell time (MDADT) method, a novel adaptive performance control scheme is proposed, which can ensure that all the variables in the system are semiglobally uniformly ultimately bounded (SGUUB) in probability and the tracking error gets into prescribed boundary no later than an arbitrarily adjusted setting time. Finally, the proposed algorithm is applied to a RLC circuit and its practicability is verified via simulation results. [ABSTRACT FROM AUTHOR]

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

In 1971, Dr. Leon Chua, known as the father of nonlinear circuits and cellular neural networks, postulated the existence of memristor, a portmanteau of memory resistor, in his seminal paper: “Memristor—The missing circuit element” published in IEEE Transactions on Circuit Theory, the predecessor of IEEE Transactions on Circuits and Systems—I: Regular Papers. In 2008, Hewlett-Packard researchers made nanomemristor devices for the first time, setting off an upsurge of memristor research. The emergence of nanomemristor devices is expected to realize nonvolatile RAM. Moreover, the integration, power consumption, and read–write speed of the RAM based on memristor are superior to those of traditional RAMs. The hardware network based on memristor synaptic devices is an important development direction of neuromorphic computing. It is a powerful technical candidate to break through the traditional von Neumann computing architecture in the post-Moore era, which will provide a feasible scheme about a technological breakthrough for surpassing Moore’s law. [ABSTRACT FROM AUTHOR]

A well-performed capacitive power transfer (CPT) system highly depends on its compensation to achieve load-independent (LI) output and zero phase angle (ZPA) operation. It is particularly meaningful to maintain these objectives under various misalignments. This paper is devoted to a general and comprehensive method to study and explore all the potential high-order compensations. The coupler parameter variation is evaluated under different types of misalignment, and misalignment-insensitive (MI) parameters are properly designed for MI resonance. A general and straightforward decomposition and synthesis method is then proposed to generate the high-order resonant tanks. With the help of inverse ABCD parameters, all tank candidates are further judged by their capability for LI output and ZPA operation. Finally, two example CPT systems are built to verify the LI output and ZPA operation under misalignment. [ABSTRACT FROM AUTHOR]

This paper proposes a new approach to above- $f_{max}$ power detection, using harmonic injection locking of a cross-coupled oscillator and the resulting change in oscillation amplitude. The paper starts with the development of a theoretical framework for this receiver. Two previous methodologies are combined: analyzing an injection-locked oscillator as an active device in a positive feedback loop with a frequency selective network; and the more recently proposed way of modeling non-linearities by using inter-harmonic translation coefficients. Using this framework, a compact equation for the expected voltage response of the receiver is derived. Finally, the design of a receiver consisting of a 200 GHz cross-coupled oscillator with a 600 GHz folded dipole antenna as its tank inductor is discussed. A Noise Equivalent Power (NEP) of 2.3 pW/ $\sqrt {\text {Hz}}$ is achieved with the proposed receiver. [ABSTRACT FROM AUTHOR]

Chaotic image encryption is widely used in the field of information security. This paper proposes a novel chaotic image encryption method with spiral-transform-based fractal sorting matrix (STFSM). First of all, the theory of STFSM with good scrambling effect is introduced, which has good irregularity and iterative. Then, the iterative algorithm and calculation example of STFSM are introduced. STFSM can be used as the map of spatial location transformations to implement the design of image encryption. Based on the complete STFSM theory and iterative algorithm, a chaotic image cryptosystem based on STFSM is proposed to achieve a good image encryption process. To test the security of the proposed algorithm, security tests and analyses such as entropy analysis, correlation analysis, resistance to differential attacks analysis, and robustness analysis are used for the proposed algorithm. The experimental analysis illustrates that the algorithm has a better encryption effect, whether using conventional tests or the attacks simulations described in this paper and can also effectively resist the attacks. [ABSTRACT FROM AUTHOR]

For a class of nontriangular nonlinear systems in presence of unknown disturbances, we propose a predictor-based neural dynamic surface control (PNDSC) strategy in this paper. This nontriangular system is transformed via the mean value theorem, and a predictor is then constructed. To avoid an algebraic loop problem, partial state vectors are employed as input signals of neural networks (NNs) for approximating unknown dynamics, and compensation items are designed to compensate for approximation errors from NNs. Different from the traditional NDSC, the PNDSC in this paper utilizes prediction errors to update learning parameters for improving NNs’ learning behaviors with overlarge adaptive gains. On the basis of improved NNs’ approximation behaviors, a predictor-based NNs disturbance observer (PNNDO) is constructed for compensation for external disturbances and approximation errors from NNs. Furthermore, with predictors, a normalization method of weights is developed to reduce the number of online learning parameters. On the basis of the aforementioned result, measurement noises are taken into account in our predictor-based neural control strategy. We employ predictor states, rather than measurement information paralyzed by noises, in design of our control strategy. This reduces high-frequency oscillations in control input. A Lyapunov-based stability analysis shows that all signals are ultimately bounded in the closed-loop system. Finally, the effectiveness of the proposed control strategy is verified by a numerical example and a permanent magnet brushless DC motor system. [ABSTRACT FROM AUTHOR]

Neural networks (NNs) with large scales of artificial neurons are increasingly used in recognition and classification tasks. In power-constrained scenarios, the tradeoff between performance and hardware consumptions must be carefully evaluated before silicon tape-out. In this paper, we proposed a systematic approach to design ultra-low power NN system. This work is motivated by the facts that NNs are resilient to approximation in many of the computations and NNs are outputting statistical tensors which are acceptable to less-than-perfect results. We resort to the front-back end approach with a twofold aim: (1) a fast and accurate design approach is proposed by estimating the computing quality of low-power approximate adder arrays, and it is adopted to evaluate the neural network system; (2) a quality configurable engine with different approximation degrees while processing NNs is implemented. The proposed work is demonstrated with a comprehensive keyword spotting (KWS) system as an ultra-low power NN engine. The experimental environment is setup with ten keywords from the google speech command dataset (GSCD) using an industrial 22-nm ultra-low-leakage (ULL) process. Comparing to the state-of-the-art KWS processors, the proposed approximate NN engine can demonstrate over 60% improvement in power efficiency and $1.1\times $ area efficiency while achieving similar recognition accuracy. [ABSTRACT FROM AUTHOR]

Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are core components in the field of signal processing. However, in the existing research, there is no fully analog circuit that can realize the one-step calculation of FFT. Therefore, in this paper, an analog circuit that can calculate FFT and its inverse transform IFFT in one-step is proposed. First, a circuit that can realize complex number operations is designed. On the basis of this structure, a fully analog circuit that can realize fast and efficient computing of FFT and IFFT in one-step is proposed. In addition, different coefficient matching can be obtained to achieve arbitrary points of FFT and IFFT by adjusting the resistance value of the memristor, which has good programmability. Specific examples are given in the paper to evaluate the proposed method. The PSPICE simulation results show that the average accuracy is above 99.98%. More importantly, the calculation speed has been greatly improved compared with MATLAB simulation. Finally, the proposed circuit can be used to quickly solve convolution operation, and the average accuracy can reach 99.95%. [ABSTRACT FROM AUTHOR]

In this paper, a Doherty power amplifier (DPA) using a novel three-port harmonic injection network (HIN) to extend its high-efficiency range is proposed. With the help of a part of the three-port HIN, which is placed between the carrier and peaking branches, the optimal drain fundamental frequency termination for the carrier device at back-off and saturation can be realized simultaneously thus enhancing the efficiency at back-off significantly. Meanwhile, this three-port HIN can also realize second harmonic drain terminations for the carrier and peaking device with the quasi-open and quasi-short circuit at the current plane, respectively. Consequently, the saturated power ratio between peaking and carrier devices is increased, which further extends the back-off range of the asymmetric drain-biased DPA. For demonstration purposes, an extended high efficiency range DPA was designed and fabricated using commercially available GaN HEMT (Cree CGH 40010F) devices. Measured results for this novel idea gave drain efficiencies better than 62.5% at 9-9.5 dB back-off point from 1.60 to 1.95 GHz. [ABSTRACT FROM AUTHOR]

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications. [ABSTRACT FROM AUTHOR]

In this paper, aiming to systematically derive single-inductor multi-input multi-output (SI-MIMO) converters having favorable merits of high-density and low-cost, a basic model is firstly extracted from the working principle. Theoretically, by enumerating all possible connections of the basic model and one-by-one manually judging their effectiveness according to working criterions, multiple viable SI-MIMO topologies can be obtained, but with heavy workload. To simplify the topology derivation process, this paper also proposes a computer-aided method to replace the manual effort. By modelling the basic model and working criterions with graph theory, MATLAB codes can be developed to automatically screen out the effective topologies. With the proposed method, 8 three-port, 28 four-port and 115 five-port converters with single inductor are conveniently obtained, including both the existing and new topologies. Moreover, by configuring ports and switches in each derived topology, multiple specific converters can be further expanded. These converters can provide more options for practical engineering applications, and a new topology is also introduced and experimentally verified in the paper. [ABSTRACT FROM AUTHOR]

This paper presents a mixed-signal SRAM-based in-memory computing (IMC) macro for processing binarized neural networks. The IMC macro consists of $128\times 128$ (16K) SRAM-based bitcells. Each bitcell consists of a standard 6T SRAM bitcell, an XNOR-based binary multiplier, and a pseudo-differential voltage-mode driver (i.e., an accumulator unit). Multiply-and-accumulate (MAC) operations between 64 pairs of inputs and weights (stored in the first 64 SRAM bitcells) are performed in 128 rows of the macro, all in parallel. A weight-stationary architecture, which minimizes off-chip memory accesses, effectively reduces energy-hungry data communications. A row-by-row analog-to-digital converter (ADC) based on 32 replica bitcells and a sense amplifier reduces the ADC area overhead and compensates for nonlinearity and variation. The ADC converts the MAC result from each row to an N-bit digital output taking 2N-1 cycles per conversion by sweeping the reference level of 32 replica bitcells. The remaining 32 replica bitcells in the row are utilized for offset calibration. In addition, this paper presents a pseudo-differential voltage-mode accumulator to address issues in the current-mode or single-ended voltage-mode accumulator. A test chip including a 16Kbit SRAM IMC bitcell array is fabricated using a 65nm CMOS technology. The measured energy- and area-efficiency is 741-87TOPS/W with 1-5bit ADC at 0.5V supply and 3.97TOPS/mm2, respectively. [ABSTRACT FROM AUTHOR]

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

Instability and oscillation issues originating in high-voltage direct current (HVDC) systems comprising modular multilevel converters (MMCs) are gaining increasing interest in the research community. To detect such phenomena in advance, considerable effort has been devoted recently to developing MMC models for small-signal analysis. The derivation of such models is a challenging task due to the topology and complex control structure of MMCs, which results in them having a multi-frequency response. To address this issue, scholars developed methods based on dynamic phasors and harmonic state-space modelling, which, however, require extensive pen-and-paper computations. In this paper, the periodic small-signal analysis (PAC) is adopted to determine numerically several MMCs transfer functions. Such functions can be computed between any electrical circuit node or input/output port, without the need to recast the three-phase average MMC model to derive a linear equivalent one, possibly in the DQ-frame. We show how vector fitting allows converting these functions to equivalent algebraic representations, which can be profitably used to design MMCs and study their stability following some parameter changes. To showcase this feature, we exploit one of these transfer functions to detect DC-side instability in a point-to-point HVDC system. [ABSTRACT FROM AUTHOR]

This paper presents a high-precision bandgap voltage reference (BGR) with high-order temperature compensation. The compensation signal is generated by using both strong-inversion MOSFETs and Bipolar Junction transistors (BJTs), which cancels the high-order nonlinear term $T\ln (T)$ in the BJT base-emitter voltage (VBE), and thus a low temperature coefficient (TC) over a wide temperature range is achieved. The proposed BGR circuit is fabricated in a 0.18- $\mu \text{m}$ CMOS process with an active area of $0.256 m{m^{2}}$ and a max power consumption of 1.35 mW. A minimum TC of 0.706 ${\mathrm{ppm}}/{}^ \circ C$ from $- 25\,\,{}^ \circ C$ to 125 ${}^ \circ C$ is achieved after an 8-bit resistance trimming. The line sensitivity is 0.0146%/V operating from 3.2 V to 3.7 V. The BGR achieves a power supply rejection (PSR) of −63.4 dB and a noise spectrum density of $0.92 ~\mu \text{V}/\sqrt {Hz} $ at 10 Hz. [ABSTRACT FROM AUTHOR]

The paper discusses the relationships between electrical quantities, such as voltages, currents, and frequency, and geometrical ones, namely curvature and torsion. The proposed approach is based on the Frenet frame utilized in differential geometry and provides a general framework for the definition of the time derivative of electrical quantities in stationary as well as transient conditions. As a byproduct, the proposed approach unifies and generalizes the time- and phasor-domain frameworks. Other noteworthy results are a new interpretation of the link between frequency and the time derivatives of voltage and current; and a definition of the rate of change of frequency that includes the novel concept of “torsional frequency.” Several numerical examples based on balanced, unbalanced, harmonically-distorted and transient voltages illustrate the findings of the paper. [ABSTRACT FROM AUTHOR]

This paper presents an improved correlation-based timing-skew calibration strategy with constant input impedance characteristics. A full sampling rate operating time-interleaved reference ADC (TI-RADC) whose interleaving factor is coprime with TI-ADC is introduced to replace the conventional single-channel reference ADC. This paper theoretically demonstrates that by setting an appropriate time interval between the sampling edge of TI-ADC and TI-RADC and aligning the sampling edge of each channel in TI-ADC with each other but not with the reference ADC, the skew of the TI-RADC would not affect the timing skew calibration of the TI-ADC. A prototype 13-bit 2-GS/s 8-way TI pipelined SAR ADC employing a 1-bit 3-way TI-RADC is fabricated in 28-nm process to verify the presented calibration strategy. Measurement results demonstrate the correctness of the calibration strategy and reveal that compared with using single-channel reference ADC operating at a decimated sampling rate, the spurs resulting from the time-variant input impedance are suppressed more than 20 dB. The prototype ADC achieves an SNDR of 60.36 dB with a near Nyquist rate input when operating at 2-GS/s. The power consumption of the prototype ADCis 252.6 mW (Including the 4.1 mW estimated digital calibration), which translates into a Walden FoM of 148.3-fJ/conversion-step. [ABSTRACT FROM AUTHOR]

In this paper, the distributed optimal containment control problem for multiple nonholonomic mobile robots (NHMRs) differential game is studied via reinforcement learning. An approximation-based optimal control strategy is developed to ensure the optimal performance index and avoid the potential collision among agents. Firstly, the collision avoidance problem considered in this paper is addressed by exploiting a consensus-like interconnection on a directed graph and an error transformation function. Then, on the basis of the optimal backstepping technique, a single critic neural network is adopted to obtain the solution of the coupled Hamilton-Jacobi (HJ) equation, in which an improved learning mechanism is constructed to relax the requirement on initial control conditions. In addition, based on the Lyapunov stability theory, it is proved that all signals in the closed-loop optimal control are uniformly ultimately bounded. Finally, the proposed control protocol is applied to NHMRs system, which verifies that the solution of the coupled HJ equation solves the containment problem of differential game. [ABSTRACT FROM AUTHOR]

Although the cyber-physical system stability is widely studied, scholars focus more on system stability with communication time delay. Therein, grid-connected inverters with the digital control system are regarded as one simplest and typical cyber-physical system. Meanwhile, the switching/sampling frequency of the inverter is always selected as low as possible from an efficiency viewpoint, resulting in unavoidable delay time. This delay time is apt to cause the system instability, which is more prone to severity under weak grid. To this end, this paper provides a minimum switching/sampling frequency for grid-connected inverters. Firstly, the system impedance model with equivalent delay time is constructed, which is based on padé approximate approach. This equivalent delay time consists of three parts, i.e., sampling delay time in cyber/physical level, calculation delay time in cyber level and pulsewidth modulation delay time in physical level, which reflects the cyber-physical interaction impact. Furthermore, the stability forbidden criterion is applied to make the switching/sampling frequency solving process become Hurwitz matrix identification problem through space mappings. Based on these space mappings, an adaptive step search approach is adopted to obtain the minimum switching/sampling frequency. Finally, the proposed approach can well evaluate the system stability under different frequencies through simulation and experiment. [ABSTRACT FROM AUTHOR]

In recent years, fast computation, low power, and small footprint are the key motivations for building SNN hardware. The unique features of SNN hardware have not been fully exploited, where the computation speed and energy efficiency of the SNN hardware can be improved according to the sparse spiking and non-uniform traffic of SNN. In this paper, we propose a 5.28-mm $^{2}~4096$ -neuron 1M-synapse energy-efficient digital SNN hardware that can achieve ultra-low energy per synaptic operation of 4.5 pJ. The proposed neuron computing unit is implemented in pipeline architecture to achieve high synaptic processing speed. The proposed spike processing unit can significantly increase the processing speed of the neuron core by $1.9\times $ and $9.4\times $ when the spike injection rate is 50% and 10%, respectively. Besides, the increase in the processing speed of the neuron core leads to a reduction in energy consumption of up to 81.5%. An event-driven clock gating circuit that can reduce the power consumption of the proposed neuron block by more than 70% is proposed in this paper. This paper proposes a supervised STDP+ algorithm for SNN training, and the classification accuracy of the MNIST digits is 89.6% with 73.6% weight sparsity of the output layer. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips. [ABSTRACT FROM AUTHOR]

Provides a listing of current staff, committee members and society officers. [ABSTRACT FROM AUTHOR]

Inhomogeneous linear ordinary differential equations (ODEs) and systems of ODEs can be solved in a variety of ways. However, hardware circuits that can perform the efficient analog computation to solve them are rarely in the literature. To address such problems, this paper proposes a general method of using a memristor-capacitor (M-C) circuit to solve inhomogeneous linear ODEs and systems of ODEs of any order in initial value problems. The M-C circuit can match the coefficients of the equations sought by adjusting the memristor resistance value according to the coefficient formula proposed in the paper, which has higher programmability. Then, some ODEs and systems of ODEs are given in the paper as examples to evaluate the proposed method. According to the comparison results based on MATLAB software simulation and the simulation based on OrCAD software, the designed M-C circuit has an effective improvement in speed and the accuracy exceeds 99.95% in software simulation. Based on practical verification, this paper gives the actual M-C circuit experiment based on PCB. Moreover, the proposed method can be used to quickly solve the object motion state in the spring mass damping system in actual engineering, and the accuracy can reach 99.98%. [ABSTRACT FROM AUTHOR]

This paper presents an overview of proximity wireless communication (PWC) technologies, their principles, design guidelines and practical applications. In particular, two different applications of PWC are reviewed. One is PWC between stacked chips. Both communication distance and coupler size are several tens of microns. Area and energy efficient design techniques are introduced. Another is PWC between module boards. Both communication distance and coupler size are several millimeters. Energy and area efficient practical designs are introduced for mobile and industrial machinery applications. [ABSTRACT FROM AUTHOR]