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Harmonic-reject mixers (HRM) are commonly used in wideband receivers to suppress the effects of spurious harmonic interferers. Both analog and digital HRMs have been proposed in the literature. In existing works, the local oscillator (LO) phases are assumed to be equally spaced. When viewed as a multiuser access system, the drawback of equally-spaced LO phases is that the signature vectors of the desired signal and some harmonic interferers become aligned, limiting the number of interferers that can be attenuated. In this paper, a digital HRM with non-uniform phase spacing that can suppress additional harmonics while being robust to gain and phase mismatches is described. This paper also presents a low-complexity, adaptive and robust digital HRM receiver that enables the fewest LOs and analog-to-digital converters necessary depending on the interference environment for low power. The performance of the adaptive non-uniformly spaced HRM is shown to be significantly superior to existing HRMs with equal LO phase spacing. [ABSTRACT FROM AUTHOR]

There is an ever increasing demand for both function integration and improved performance in wireless communication devices. Therefore, the integration of efficient linearizing amplifying and bandpass filtering functions is proposed for the first time in this paper. A new Doherty amplifier configuration with attractive behaviors including bandpass filtering, wideband harmonic suppression, and enhanced efficiency, is presented. A component crucial to the successful implementation of the proposed configuration is the bandpass quadrature coupler with arbitrary coupling coefficient. Owing to the flexibility of a circular patch in locating the frequencies of different operational modes, it is thus possible to implement good bandpass characteristics. With the introduction of this new component, the Main and Auxiliary amplifiers can be driven more efficiently, resulting in both linearity and efficiency improvements. To verify the validity of the proposed configuration, a Doherty amplifier has been designed and fabricated. Its measured performance is compared with the conventional design and found to exhibit a bandpass filtering characteristics with a wide suppression band up to the third harmonic frequency. Meanwhile, the proposed amplifier achieves a measured power-added-efficiency improvement of 10% and an ACLR improvement better than 5.8 dB at the higher output power region. [ABSTRACT FROM PUBLISHER]

This paper analyzes the effect of operational amplifier (OPAMP) input offset on continuous-time (CT) delta-sigma (\Delta\Sigma) modulators with current-mode feedback digital-to-analog converters (DAC). Our analysis shows that the input offset leads to either increased harmonics or increased noise floor of the modulator, depending on whether a DAC shuffling scheme, such as data-weighted averaging (DWA), is applied or not. Analysis and mathematical derivation are given and verified by transistor-level simulations. An input-offset cancellation scheme is proposed and demonstrated by simulation results. [ABSTRACT FROM AUTHOR]

In this paper, analysis and synthesis approach for two new variants within the Class-EF power amplifier (PA) family is elaborated. These amplifiers are classified here as Class-E3F and transmission-line (TL) Class-E3F2. The proposed circuits offer means to alleviate some of the major issues faced by existing topologies such as substantial power losses due to the parasitic resistance of the large inductor in the Class-EF load network and deviation from ideal Class-EF operation due to the effect of device output inductance at high frequencies. Both lumped-element and transmission-line load networks for the Class-E3F PA are described. The load networks of the Class-E3F and TL Class-E3F2 amplifier topologies developed in this paper simultaneously satisfy the Class-EF optimum impedance requirements at fundamental frequency, second, and third harmonics as well as simultaneously providing matching to the circuit optimum load resistance for any prescribed system load resistance. Optimum circuit component values are analytically derived and validated by harmonic balance simulations. Trade-offs between circuit figures of merit and component values with some practical limitations being considered are discussed. [ABSTRACT FROM PUBLISHER]

This paper focuses on anomalous nonlinear phenomena in a thyristor controlled reactor-static var compensator (TCR-SVC) system, called switching time bifurcation, and clarifies the relationship between the occurrence of nonlinear phenomenon and the intrinsic characteristics of the circuit equation with switching function. The occurrence of nonlinear phenomenon in a TCR-SVC system cannot be predicted when the dynamics of the circuit related to the switching action is neglected. Therefore, this paper considers the dynamics related to the switching operations in the analysis of nonlinear phenomena. The parametric excitation of circuit is discussed in relation to the homogeneous expression of the circuit equation. This paper indicates that the homogeneous equation of the TCR-SVC system results in Hill's equation, and it can be approximated as Mathieu's equation. The occurrence of nonlinear phenomena in the system is evaluated using the characteristics of Mathieu's equation. The anomalous nonlinear phenomena occur when the natural frequency of Mathieu's equation coincides with the frequency of the ac voltage in a TCR-SVC system. The parametric excitation is also confirmed through the characteristics of Hill's equation. This study clarified the interaction between the switching dynamics of the circuit and its external excitation, and clued the occurrence of nonlinear phenomena in the circuit. The proposed procedure can also be applied to the analysis for other switching converter circuits with periodic excitation source. [ABSTRACT FROM AUTHOR]

In this paper, a switched load harmonic rejection mixer (HRM) structure with one single mixer core and a pair of switched load resistors is proposed. Different from the traditional three-phase HRM which is widely used in DTV tuners, this HRM performs the harmonic rejection function by vector multiplication rather than superposition. Sharing most of its parts with an ordinary Gilbert mixer, the proposed HRM shows greater simplicity in structure. The single mixer-core structure is also more power efficient than a traditional three-phase HRM. In order to verify the effectiveness of this approach, a proof-of-concept prototype is designed and fabricated in 0.18-\mum RFCMOS technology. Measurements indicate that 38 dB for 3rd and 34.5 dB for 5th harmonic rejection ratio can be achieved. The HRM including a buffer stage consumes a low bias current of 3 mA under 1.8 V supply voltage and has equivalent performance such as CG, NF, and IIP3 to an ordinary Gilbert mixer. With the load switch inactivated, this HRM can be easily transformed into an ordinary Gilbert mixer, which increases its flexibility for different applications. [ABSTRACT FROM AUTHOR]

Scaled CMOS proves to be suitable for the design of transceiver ICs at micro- and millimeter-waves. The effort is presently toward compact and low-power solutions in view of integrating several transceivers on the same chip enabling phased array systems. In this paper we present a 24 GHz receiver, based on a subharmonic direct conversion architecture, designed in a 65 nm node. The local oscillator takes advantage of the half frequency operation proving significantly lower power consumption when compared to conventional solutions running at received frequency. Stacked switches for subharmonic down-conversion are passive to save voltage room, current driven and loaded by a transresistance amplifier. Optimum biasing of the switches allows maximizing linearity while saving power in the baseband. The integrated LNA matching network is the bottleneck toward low sensitivities. The LNA design trades-off power consumption, gain and sensitivity. Detailed insights into implementation issues, critical in a single-ended topology where both forward and return signal paths have to be supported, are provided. The chip consumes 78 mW and occupies 1.4 mm^2 of active area. Experiments show: 30.5 dB gain, 6.7 dB NF, -13 dBm IIP3. [ABSTRACT FROM PUBLISHER]

In this paper, a generalization of the concept of electrical power for periodic current and voltage waveforms based on a new generalized complex geometric algebra (GCGA) is proposed. This powerful tool permits, in n-sinusoidal/nonlinear situations, representing and calculating the voltage, current, and apparent power in a single-port electrical network in terms of multi vectors. The new expressions result in a novel representation of the apparent power, similar to the Steinmetz's phasor model, based on complex numbers, but limited to the purely sinusoidal case. The multivectorial approach presented is based on the frequency-domain decomposition of the apparent power into three components: the real part and the imaginary part of the complex-scalar associated to active and reactive power respectively, and distortion power, associated to the complex-bivector. A geometrical interpretation of the multivectorial components of apparent power is discussed. Numerical examples illustrate the clear advantages of the suggested approach. [ABSTRACT FROM AUTHOR]

This paper proposes a novel push-pull Class-E series-parallel resonant power amplifier (PA), which parallels two basic one-inductor, one-capacitor Class-E high-efficiency switching-mode tuned PA (Sokal, 1981) circuits. This proposed topology utilizes a push-pull scheme to realize sinusoidal output voltage. The previously published Class-E circuits (Sokal, 1981) can be implemented in a very simplified circuit. However, the simplified circuit is only appropriate for applications in which the harmonic content of output is not an important criterion. The proposed amplifier with two series-parallel resonant load networks will allow sinusoidal output voltage to be achieved by associating with the positive and negative quasi-sinusoidal waveforms. The complementarily activated configuration will provide continuous high-ripple-frequency input-current waveforms; this approach significantly reduces electromagnetic interference and requires very little filtering. With the symmetry of the push-pull Class-E circuit, there is the additional benefit that the even harmonics are suppressed at the load, and thus there are fewer harmonic distortions. However, each switch is symmetrically driven with a duty ratio of less than 0.5 to meet the nominal Class-E operating conditions, which leads to a narrower operating frequency variation. A prototype of the proposed PA shows over 95% efficiency at 48-V input, with 18-W output and an operating frequency of 900 kHz [ABSTRACT FROM PUBLISHER]

It is well known that in balanced (or differential) circuits, all even harmonics are canceled. This cancellation is achieved by using two paths and exploiting phase differences of 1800 between the paths. The question addressed in this paper is: what distortion products (harmonics and intermodulation products) are canceled if more than two paths (and phases) are used? These circuits are called polyphase multipath circuits. It turns out that the more paths (and phases) are used, the more distortion products are canceled. Unfortunately, some intermodulation products cannot be canceled without also canceling the desired signal. An analysis of the impact of mismatch between the paths shows that the suppression of distortion products will be larger if more paths are used. As an application example, the design of an upconversion mixer with a clean output spectrum is presented. [ABSTRACT FROM AUTHOR]

In this paper, analysis and design for a single-phase active power filter (APF) with one-cycle control is presented. The proposed control method eliminates the need of sensing the load current, a nontrivial task of calculating the harmonics and reactive current components, as well as the use of multipliers, as reported by many previously reported approaches. In addition, the switching loss is reduced by employing unipolar operation, where only two out of four switches are operated at switching frequency while the other two are stationary on or off during an entire half- line cycle. The design methodology taking electromagnetic interference filter into account is also discussed in detail. The theoretical analysis is verified by experiments. [ABSTRACT FROM AUTHOR]

Multilevel pulsewidth modulation (PWM) has become very important in high-power applications in recent years. Many different types of topology and control strategy have been developed to cater for the increasing need. One of the major concerns of the control strategy is to reduce the undesirable harmonics in order to improve the performance and efficiency. This paper presents the derivation of analytical solutions for determining the spectral characteristics of the multicarrier-based multilevel sinusoidal PWM. By decomposing the multilevel PWM into a series of sub-PWM and followed by using double Fourier series analysis, compact analytical solutions for any level with any carrier phase disposition have been obtained. Closed-form solutions have also been derived for double-sided multilevel PWM under certain specific carrier phase settings. The analytical solutions have been cross verified extensively with simulations and the results match with each other very well. It is shown that the proposed analytical solutions are by far the most compact reported in the literature. [ABSTRACT FROM AUTHOR]

In this paper, a class of passive mixer-first, LNA-less receivers is analyzed in depth. Quadrature passive mixers are shown to present the impedance of their baseband port to the RF port and vice versa. This transparency property, in combination with resistive feedback differential amplifiers, and “complex” feedback between the I and Q paths, can be used to control the impedance at the RF port. This impedance can be tuned using only baseband components (i.e., resistors). The noise limits of such an architecture are analyzed and simulated, and are shown to be comparable to standard RF-LNA-first receivers. Accounting for the higher harmonics of the LO frequency proves critical in accurately analyzing the behavior of these circuits and their ability to provide an impedance match with low noise figure. Additionally, it is shown that expanding quadrature passive mixers to harmonic rejection mixers allows for even better noise performance and wider matching range. [ABSTRACT FROM PUBLISHER]

In this paper, a repetitive-based controller for a boost- based power factor precompensator is presented. The controller guarantees voltage regulation with a power factor close to unity, despite of the presence of harmonic distortion in the source voltage and uncertainties in the system parameters. It is shown that the repetitive scheme considered here is, in fact, equivalent to a bank of resonant filters, which has shown to be a useful technique in harmonic compensation. Out of this equivalence, a negative feedback structure is obtained for the repetitive scheme which is aimed for the compensation of odd harmonics only. This is in contrast to usual positive feedback repetitive schemes aimed to compensate for all harmonic components. The repetitive scheme consists on a simple feedback array involving a time delay plus a feed forward path, which is simple to implement. The closed-loop stability analysis of such and infinite-dimensional system is performed appealing to the well-known small gain theorem. Experimental resuIts in a 400-W boost-based power factor compensator (PFC), with a fixed-point digital signal processor (DSP)-based implementation of the proposed controller, are provided to assess the performance of the controlled system. [ABSTRACT FROM AUTHOR]

This paper presents intuitive yet quantitative insights into the harmonics of analog-to-digital converter (ADC) output spectra. It derives the spectral signatures associated with imperfections in practical ADCs. This understanding leads to remedies based on architecture and time-averaging, which are combined to propose a calibration-free pipeline CMOS ADC that simulations show is capable of better than 100-dB spurious-free dynamic range in the presence of real-life imperfections. [ABSTRACT FROM AUTHOR]

A high-Q, tunable, bandpass filtered amplifier structure is proposed which is based on a novel Q enhancement technique in N-path filters. Using Fourier series analysis, frequency response of an N-path filter as well as the aliasing effects which are present in it are derived. Frequency translation of unwanted contents at higher frequencies to the center frequency of the bandpass filter is called harmonic fold back (HFB). It is shown that using an additional N-path filter with the same clock frequency but different clock phases can reduce the HFB. The required conditions for fold back elimination are derived from Fourier series expansion analysis. In order to achieve HFB reduction as well as increasing stop-band rejection and Q factor, an LNA containing an N-path filter is added to each of the two filters. The LNA in the proposed structure is designed for high linearity and low NF, utilizing noise and distortion cancellation methods. The filter is designed and simulated in 0.18 um CMOS with an ideal balun. The voltage gain is 17.5 dB across the 0.25–1 GHz frequency band, while achieving a NF between 2.2 to 2.4 dB, an IIP3 between -2 to +2 dBm, HFB attenuation of between 25 to 45 dB and power consumption of 4.5 mW for each LNA. Finally, the proposed filter (with 4-path sub-filters) is simulated and compared to filters with 4-path and 8-path sub-filters without the proposed built-in HFB reduction. [ABSTRACT FROM PUBLISHER]

The behavior of LC-CMOS frequency dividers is investigated in depth obtaining a new and clearer insight into the synchronization phenomenon. We show that it occurs according to two mechanisms, which are referred to as “synchronization by mixing” and “synchronization by harmonics.” This latter, still not known, may be the dominant mechanism in some practical circuits, and justifies the presence of locked states when the well known mechanism by mixing fails to predict them. A new model of CMOS frequency dividers that includes both mechanisms is presented, and its utility is demonstrated by analyzing the locked states of a divider by 3 and of a divider by 4, which are predicted in closed form. The calculation results show a close correspondence between the theory and the circuit simulations and measurements. [ABSTRACT FROM PUBLISHER]

A family of algorithms based on a two-step Galerkin's method for approximating the solution of steady state problems formulated in the frequency domain are presented. Such methods work by reducing the number of unknowns of the conventional harmonic balance (hb) method. With respect to the state-of-the-art hb algorithm via gmres, the new algorithms lead to better convergence properties, reduced memory occupation and the ability to achieve acceptable approximations of the solution at reduced computational time. In this way the new approach allows analyzing circuits described by models that involve up to hundred thousands electrical unknowns. As a by-product, is it shown that the heuristic oversampling technique, which is largely used in hb commercial simulators, is here easily formalized as one step of the proposed methods and a profitable way to improve it is presented. [ABSTRACT FROM AUTHOR]

An analysis of the Class-E power amplifier is given using harmonic modeling that facilitates its characterization for a wide load-space regime expected in applications such as RF plasma generation for semiconductor manufacturing. Using a hybrid matrix- framework made up of the dominant harmonics of the circuit variables aided by the time-domain boundary conditions of the power switch voltage waveform, a quasi-linear algorithm is developed to accurately determine the voltage and the current levels expected on all components of the power amplifier for arbitrary loading and operating conditions. The application of the algorithm for design optimization is discussed, and its extension to phase-controlled Class-E power amplifier pairs is described. [ABSTRACT FROM AUTHOR]