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This paper presents a digital battery management unit (BMU) with built-in resistance (BIR) compensation, modulated frequency detection (MFD), and multi-mode protection (MMP) techniques to realize fast, efficient and safe charging. The charger incorporates the proposed BMU based on the low-dropout (LDO) regulator. With BIR compensation, a large rated current in the proposed pulsed constant current (PCC) mode charges the battery, and reduces the charging time by omitting the constant-voltage (CV) mode. The MFD technique allows continuous monitoring and obtains precise BIR compensation with accelerating sampling speed. The MMP technique can alleviate safety concerns while charging, including over-voltage protection (OVP), over-current protection (OCP), and the proposed accidental fluctuation protection (AFP). The digital BMU, implemented in 28 nm CMOS, occupies 0.014 mm2 of silicon area. Experimental results show that the proposed circuit saves 73.3% of charging time with 1.5A charging current, and 21.5% ADC dynamic power with 1A charging current. For the digital controller IC, the power consumption is $59.1~\mu \text{W}$. [ABSTRACT FROM AUTHOR]

This paper presents a filtering power amplifier (PA) with wide bandwidth. A bandpass filter (BPF) using discriminating coupling is first proposed to be utilized as the output matching network (OMN) of PA. Discriminating coupling means that the fundamental and the harmonics of the proposed structure have different coupling coefficients. Thus, the input impedances of the fundamental, second and third harmonics could meet the requirements of the extended continuous mode theory, respectively. Also, good frequency selectivity is obtained. The working principle of discriminating coupling, the filter synthesis theory and the equivalent circuit are utilized to guide the design of the filtering PA. To demonstrate the proposed structure, a compact filtering PA operating at 1.8 GHz is designed. The measured results exhibit good frequency selectivity and high power added efficiency (PAE). More importantly, comparing to the previous filtering power amplifiers (PAs) with good frequency selectivity, the proposed design possesses wide bandwidth of 31.1% with PAE higher than 60%. [ABSTRACT FROM AUTHOR]

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This paper presents a digital readout integrated circuit (DROIC) for small pitch medium-wave infrared (MWIR) starring focal plane arrays (FPAs). To overcome the limited in-pixel resolution of such DROICs, the concept of error shaping is introduced in pulse frequency modulation (PFM)-based pixels. Multiple integration operations are performed in a single frame and the residue charge from each integration phase is retained and injected into the next charge packet. This over-integration routine provides a high pass noise transfer function (NTF) equivalent to what is obtained in a first order sigma delta modulator. The concise structure of a PFM analog-to-digital converter (ADC) lends itself well to such an operation inside the pixel, while consuming low power. Along with a theoretical analysis of the technique, a prototype based on a $16\times 16$ array and sinc decimation filters is developed to demonstrate the performance of the proposed DROIC. With an in-pixel resolution of 5 bits and over-integration ratio (OIR) of 128, 395 noise electrons are demonstrated at full-well fill from the test array fabricated in a 90 nm bulk-CMOS process. [ABSTRACT FROM AUTHOR]

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A table of contents for the issue is presented including regular papers on various topics such as Analog and Mixed Mode Circuits, Control Theory and Systems and Signal Processing, comments and information for authors.

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This issue includes selected papers presented at the IEEE Asia Pacific Conference of Circuits and Systems (APCCAS) 2018 that was held in Chengdu, China, on 26–30 October 2018 and the IEEE International Conference on Electronics, Circuits and Systems (ICECS) 2018 that was held in Bordeaux, France, on 9–12 December 2018. As the flagship conferences of the IEEE Circuits and Systems Society (CASS) in IEEE Regions 8 and 10, respectively, these conferences welcome contributions across the themes within the scope of the Society, including analog, digital and mixed-signal electronics, signal processing, power electronics, communication theory, sensors, circuit theory, and nonlinear circuits and systems. [ABSTRACT FROM AUTHOR]

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This paper proposes an LCCC and CCL compensated wireless servo motor control circuitry utilizing the merits of fundamental and third harmonic. With this circuitry, the motor side needs no additional power supply and controller, which significantly reduces the difficulty of maintenance. Besides, benefiting from the proposing of CCL compensating topology and utilizing of the self-driven circuitry, the secondary operates in fully resonant state and the motor direction control H-bridge is self-driven by the LC frequency selecting circuitry (FSC). Moreover, compared with the conventional motor control circuitry, because of the use of fundamental and third harmonic, the power equalization becomes significantly easier, and zero voltage switch (ZVS) can be realized at the same time; Besides, motion direction control of the motor is simpler with only a single pole double throw (SPDT) at the transmitter side. In addition, system resource consumption is reduced compared with conventional motor drive topologies. In this paper, an 180W prototype is built for experimental verification, and the result shows a good power equalization capability and a transfer efficiency reaching up to 90% at the distance of 10cm. [ABSTRACT FROM AUTHOR]

To comply with IEEE copyright policy, authors are requiredto sign an IEEE Copyright Form beforepublication. B) Manuscript Format: Manuscripts must follow the standard single-spaced, double-column IEEE Transactions format, as specified at http://www.ieee.org/ publications standards/publications/authors/authors journals.html.Seealsohttp://www.ieee.org/publications standards/publications/authors/author templates.html forstyle filesand templates to guide the typesetting of the paperfor submission. If the voluntary page charge is not honored, IEEE will charge a mandatory page charge of $125 per page for each page in excess of 11 pages (including referencesand biographies). [Extracted from the article]

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Welcome to the 2017 Special Issue on the IEEE Circuits and Systems Society (CASS) Regional Flagship Conferences, a collection of selected papers presented at the 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2016), held in Jeju, South Korea, October 25–28, 2016, the 23rd IEEE International Conference on Electronics Circuits and Systems (ICECS 2016), held in Monte Carlo, Monaco, December 11–14, 2016, and the 8th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2017), held in Bariloche, Argentina, February 20–23, 2017. In APCCAS 2016, 212 papers were presented, selected from 310 papers submitted; in ICECS 2016, 191 papers were presented, selected from 353 papers submitted; in LASCAS 2017, 70 papers were presented, selected from 172 papers submitted. [ABSTRACT FROM AUTHOR]

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