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Large-scale risk events in the venture capital (VC) market can easily lead to systemic risk in the financial market. This paper collects the comprehensive dataset of Chinese VC market from 1999 to 2020, and constructs the multi-layer networks of VC market. After that, a risk contagion model of venture capital market is designed considering both the capital loss transmission and social relations effect (investor herd behavior). By simulating various situations with different risk origins and scales, the speed of risk contagion and the total impacts on the overall stability of the market (network) are compared. We find that the herd behavior of the market will generally aggravate the consequences of risk contagion. Compared with unicorns, the failure of a leading VC firm can cause a wider range of risk contagion. The contagion consequences caused by the failure of random financing companies are more serious than those caused by random VC firms. Moreover, we identify that telecommunications services and information technology are high-risk industries in VC market. Based on the empirical results, this article provides policy implications for the market regulatory sectors to prevent VC market risks. [ABSTRACT FROM AUTHOR]

This paper presents the theory of a novel memcomputing paradigm based upon a memristive version of standard Cellular Nonlinear Networks. The insertion of a nonvolatile memristor in the circuit of each cell endows the dynamic array with the capability to store and retrieve data into and from the resistance switching memories, obviating the current need for extra memory blocks. Choosing the parameters of each cell circuit so that the memristors may undergo solely sharp transitions between two states, each processing element may be approximately described at any time as one of two first-order systems. Under this assumption, the classical Dynamic Route Map may be employed to synthesise and analyse the data storage and retrieval genes. A new system-theoretic methodology, called Second-Order Dynamic Route Map, is also introduced for the first time in this paper. This technique allows to study the operating principles of arrays with second-order processing elements, as is the case, in the proposed network, if the set up of cell circuit parameters induces analogue memristive dynamics. This paper shows how the novel tool may be adopted to investigate the operating mechanisms of a cellular array with second-order cells, which compute the element-wise logical OR between two binary images. [ABSTRACT FROM AUTHOR]

Video processing requires an increasing amount of buffered data. The paper proposes a multi-line buffer circuit that stores compressed data thus saving logic and power. The lossy compression algorithm provides the output stream with a fixed, decided by the user, delay from the input stream. Further, the amount of memory of the compressed buffer can be designed to trade off the correctness of the output with the logic resources footprint. The circuit is tested in a computer vision processing chain as a binary line buffer for the stream of foreground pixels. The paper also proposes a multi-line buffer circuit that integrates a morphological operation. The latter, when compared against the state of the art and against the proposed multi-line lossy buffer, allows larger saving of logic resources (up to 75%) and power (up to 85%), with reduced penalty on video quality. [ABSTRACT FROM AUTHOR]

In this paper, we present the first implementation of a 1 million-point fast Fourier transform (FFT) completely integrated on a single field-programmable gate array (FPGA), without the need for external memory or multiple interconnected FPGAs. The proposed architecture is a pipelined single-delay feedback (SDF) FFT. The architecture includes a specifically designed 1 million-point rotator with high accuracy and a thorough study of the word length at the different FFT stages in order to increase the signal-to-quantization-noise ratio (SQNR) and keep the area low. This also results in low power consumption. [ABSTRACT FROM AUTHOR]

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

The present manuscript relies on the companion paper entitled “Memristor Circuits: Flux–Charge Analysis Method,” which has introduced a comprehensive analysis method to study the nonlinear dynamics of memristor circuits in the flux–charge $(\varphi ,q)$ –domain. The Flux–Charge Analysis Method is based on Kirchhoff Flux and Charge Laws and constitutive relations of circuit elements in terms of incremental fluxes and incremental charges. The straightforward application of the method has previously provided a full portrait of the nonlinear dynamics and bifurcations of the simplest memristor circuit composed by a capacitor and a flux-controlled memristor. This paper aims to show that the method is effective to analyze nonlinear dynamics and bifurcations in memristor circuits with more complex dynamics including Hopf bifurcations (originating persistent oscillations) and period–doubling cascades (leading to chaotic behavior). One key feature of the method is that it makes clear how initial conditions give rise to bifurcations for an otherwise fixed set of circuit parameters. To the best of the authors’ knowledge, these represent the first results that relate such bifurcations, which are referred to in the paper as Bifurcations without Parameters, with physical circuit variables as the initial conditions of dynamic circuit elements. [ABSTRACT FROM AUTHOR]

This paper considers the condition when a rational function $F(s)$ may be represented as the function of the argument $s+(1/s)$ . If this condition is satisfied then $F(s)$ is the ratio of recursive (symmetric) polynomials. This paper investigates the network properties of such rational functions and their realization. Then the symmetric polynomials are applied for synthesis of symmetric band-pass filters. Substituting $p=s+(1/s)$ into symmetric band-pass filter transfer function one obtains its low-pass generating filter. The slew rate and overshoot of generating filter step-response is closely connected with the step-response duration of symmetric band-pass filter. The choice of generating filter becomes an additional factor of symmetric band-pass filter design. As the generating filters the paper proposes using Lommel polynomial filters which have easy control of overshoot and slew rate. An example of six order symmetric band-pass filter is given. [ABSTRACT FROM PUBLISHER]

This paper is concerned with the problem of event-triggered optimized control for uncertain nonlinear Itô-type stochastic systems with time-delay and unknown dynamic. By using fuzzy logic systems to approximate two unknown nonlinear functions with the delayed state and current state, respectively. The adaptive identifier is constructed to determine the stochastic system, and the optimized control is designed by using the identifier and adaptive dynamic programming (ADP) of actor-critic architecture. Almost all of the works are concentrated on ADP-based optimal control and it will inevitably cause the complexity of computation and requirements of persistence excitation (PE) assumption. In this paper, the ADP algorithm is obtained based on the negative gradient of a simple positive function (equivalent to the HJB equation), and so the proposed optimal control is simple and can release the PE assumption. Moreover, the event-triggered control approach is proposed to reduce computing burden and communication resources. Furthermore, we prove that the states of system and FLSs parameter errors are semi-globally uniformly ultimately bounded (SGUUB) in mean square via the adaptive identifier and the Lyapunov direct method as well as identifier-actor-critic architecture-based ADP algorithm. Finally, the effectiveness of the proposed method is illustrated through two numerical examples. [ABSTRACT FROM AUTHOR]

This review paper presents an overview of readout architectures and analog-to-digital converters (ADCs) for 3D-stacked CMOS image sensors (CIS) with their advantages and challenges. Depending on the application requirements, a suitable 3D-stacked readout architecture will be proposed. While most ADCs to date have been reported in planar CIS, this paper ports these designs to a 3D-stacked CIS and compares the different ADC topologies for this 3D-stacked context in terms of noise, speed and power efficiency. The comparison shows that the ramp and incremental ΔΣ (IΔΣ) ADCs can achieve a better overall performance compared to the SAR and cyclic ADCs by a factor of ~3 better for 3D-stacked CIS. In addition, ramp and IΔΣ ADCs can both achieve (very) low fixed-pattern noise values. [ABSTRACT FROM AUTHOR]

The article offers information on the criteria's for submission of research papers to the journal which includes topics on circuits and systems for communications, signal processing and control theory in circuits and system.

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

The article offers brief information on the journal including manuscript length, Circuits and Systems for Communications (COMM) and Submission of a Paper, for authors.

The article presents information for authors for publishing articles in the journal. The journal expect to receive papers which focus on circuit theoretic methodologies in their analysis/design, which present results in integrated circuit implementation. The papers which do not follow recommendation will be returned to the authors.

This paper presents a single-stage tri-path buck converter with reduced inductor current and self-balanced flying capacitor voltage. The proposed converter introduces capacitor paths to reduce the average inductor current and inductor current ripple, hence decreasing the conduction loss. Operating with two states per conversion cycle, it exhibits a relatively low voltage conversion ratio of ${D}$ /(1 $+\,\,2{D}$). Besides, it realizes a self-balanced flying capacitor voltage in the charge redistribution phase. Similar to the conventional buck converter, the proposed converter in continuous-current mode only has two complex poles. Therefore, we design a Type-III compensator to obtain a good transient response. Moreover, the circuit does not require extra supplies for gate drivers due to the reutilization of the flying capacitor voltages, eliminating additional circuit and power overheads. The proposed converter, validated in a 65-nm standard CMOS technology, regulates a 0.7 V – 1 V output voltage from a 3.3 V – 4 V input voltage, delivering a maximum output power of 270 mW. The peak efficiency is 84%, with a switching frequency up to 5 MHz. [ABSTRACT FROM AUTHOR]

Eight-switch three-phase post-fault inverter (ESTPI) is widely used as the reconfigured topology of three-phase three-level neutral point clamped DC/AC inverter when open-circuit fault occurs. A key technical challenge for the ESTPI is the post-fault controller design. The existing post-fault control approaches for the ESTPI suffer from the difficulty in trading off the current tracking performance, neutral point voltage (NPV) balancing and common mode voltage (CMV) levels. To solve this problem, this paper proposes an improved predictive current control algorithm. The proposed algorithm contributes to achieve accurate output current tracking while greatly reducing the CMV with a balanced NPV. Simulation and experimental results are presented to validate the effectiveness of the proposed algorithm. [ABSTRACT FROM AUTHOR]

In this paper, the consensus problem for a class of second-order multi-agent systems under aperiodically intermittent communication is investigated. First, a new sampled-hold-based intermittent control protocol is designed to achieve consensus and improve the consensus performance in the absence of continuous communication. Then, some necessary and sufficient conditions are obtained for second-order consensus based on the relationship of the control gains, the eigenvalues of the Laplacian matrix, and the intermittent communication architecture. Moreover, if the sampled-hold-based aperiodically intermittent control is degenerated into the aperiodically intermittent control or the sampled-hold-based periodically intermittent control, some simpler consensus conditions are also given. Finally, some experimental simulations are shown to verify the correctness of the theoretical analysis. [ABSTRACT FROM AUTHOR]

In this paper, the dual common-mode (CM) resonance technique is proposed for lowering the phase noise (PN) and flicker PN corner of LC voltage-controlled oscillators (VCOs) across wide tuning range. The dual CM resonator can provide high and resistive input impedance across a wide $2^{\mathbf {nd}}$ harmonic band without dedicated tuning. It can both prevent the tank-loading effect and reshape the output waveform. Novel implementation methods are demonstrated to realize dual CM resonance at high frequencies. For comparison, both the dual CM resonance VCO and a reference one with a tail filter are fabricated in 65-nm CMOS, achieving the measured frequency range of 8-11.15 and 7.98-11.3 GHz, respectively. In 1/f2 region, the proposed VCO shows an average PN of −139 dBc/Hz and the FOM of 190-192.3 dBc/Hz across the band, leading to an excellent FOM $_{\mathbf {T}}$ of larger than 200.3 dBc/Hz. The reference VCO shows the average PN and FOM of -137.7 and 190.5 dBc/Hz. In 1/f3 region, the former exhibits a low flicker PN corner of 280–350 kHz while the latter’s flicker PN corner varies largely from 290 to 950 kHz across the band. Both VCOs’ cores consume about 5 mW at 1 V supply and occupy approximately 0.13 mm2. [ABSTRACT FROM AUTHOR]

Modern NVIDIA GPU architectures offer dot-product instructions (DP2A and DP4A), with the aim of accelerating machine learning and scientific computing applications. These dot-product instructions allow the computation of multiply-and-add instructions in a single clock cycle, effectively achieving higher throughput compared to conventional 32-bit integer units. In this paper, we show that the dot-product instruction can also be used to accelerate matrix-multiplication and polynomial convolution operations, which are widely used in post-quantum lattice-based cryptographic schemes. In particular, we propose a highly optimized implementation of FrodoKEM wherein the matrix-multiplication is accelerated by the dot-product instruction. We also present specially designed data structures that allow an efficient implementation of Saber key-encapsulation mechanism, utilizing the dot-product instruction to speed-up the polynomial convolution. The proposed FrodoKEM implementation achieves $4.37\times $ higher throughput than the state-of-the-art implementation on a V100 GPU. This paper also presents the first implementation of Saber on GPU platforms, achieving 124,418, 120,463, and 31,658 key exchanges per second on RTX3080, V100, and T4 GPUs, respectively. Since matrix-multiplication and polynomial convolution operations are the most time-consuming operations in lattice-based cryptographic schemes, we strongly believe that the proposed methods can be beneficial to other KEM and signatures schemes based on lattices. [ABSTRACT FROM AUTHOR]

A new active building block namely, subtractor connected first-generation current conveyor (S-CCI) is introduced in this paper. A simulated floating inductor (SFI) and two new quadrature oscillators (QOs) employing only one S-CCI are introduced as application examples. The introduced SFI employs two resistors with a single matching requirement and a grounded capacitor. Each of the introduced QOs has one grounded resistor, one floating resistor, and two grounded capacitors without any matching problems. Non-ideality analyses are performed. Furthermore, a third-order filter application is given. A layout of the S-CCI in $0.18 \mu \text{m}$ technology occupying the area of about $71\,\,\mu \text{m}\,\,\times 44\,\,\mu \text{m}$ is given. Also, numerous post layout simulations based on the SPICE program are accomplished. Moreover, several experiments are realized to confirm the theory. [ABSTRACT FROM AUTHOR]

This paper presents a performance analysis of a system for electrochemical impedance spectroscopy (EIS). The system, composed by an analog front-end (AFE) and a custom microcontroller (MCU) board, performs the impulse response (IR) measurement of linear and time-invariant (LTI) systems with pseudo-random excitation signals. As a novelty, a specific AFE for the interfacing of two-terminal resistive and capacitive sensors is covered in detail. The paper proposes, for the first time, a mathematical model to predict the impact of the main noise sources in the measured IR. Thanks to the proposed approach, the AFE and the system’s parameters can be properly designed in order to reduce the error, thus, minimizing the energy-per-error figure of merit (FOM) as well. The AFE is realized as discrete-components circuit and it has been included in a custom MCU-based measurement system as an expansion module. The predicted results from the mathematical model, in terms of noise power, SNR, and measurement error are validated through system-level simulation and experimental measurements. The system performs the IR measurement with 1023 points, showing root-mean-square (RMS) measurement errors of 1% and 1.4% for the tested ADC sampling frequencies of 62.5 kHz and 125 kHz, respectively. These lead to excellent FOM values of 128.9 mJ $\cdot $ %2 and 252.6 mJ $\cdot $ %2 that outstand the state of the art. [ABSTRACT FROM AUTHOR]

In this paper, a novel saturation-based control method is proposed for high-order sliding mode (HOSM) dynamics with upper-triangular nonlinearities. Firstly, a new HOSM dynamics with upper-triangular nonlinearities is constructed based on the traditional HOSM dynamics, so as to reduce the uncertainties in the control input channel. Then, a HOSM controller is established by means of the adding a power integrator method such that the new HOSM dynamics is locally stabilized. Finally, the saturation-based controller is constructed by a combination of the saturation technique and the local HOSM controller to guarantee that the sliding variables can converge into a domain of attraction in a finite time and retain inside it thereafter. The rigorous stability analysis is made by the Lyapunov theory. A simulation example is also given to demonstrate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density (and therefore resolution) over that of speed, where the most widely used refresh rates fall between 25–240 Hz. Therefore, memristor-CMOS logic is a promising fit for peripheral I/O logic in active matrix displays. In this paper, we design and implement a ternary 1–3 line decoder and a ternary 2–9 line decoder which are used to program a seven segment LED display. SPICE simulations are conducted in a 50-nm process, and the decoders are synthesized on an Altera Cyclone IV field-programmable gate array (FPGA) development board which implements a ternary memristor model designed in Quartus II. Our approach to logic synthesis demonstrates a potential way forward for simulating large-scale memristor-CMOS circuits without embedded RRAM for functional verification, and our SPICE results show an improvement in data density of a variety of decoders by a factor between 3.6-8.5. While the switching speed of memristors are one of several bottlenecks to using them in combinational logic, the comparatively slow refresh rates of typical microdisplays indicate this to be a tolerable trade-off, which promotes data density over speed. [ABSTRACT FROM AUTHOR]

This paper presents a Doherty power amplifier (DPA) with reduced size and wide bandwidth by using a simplified output matching topology. In broadband DPA designs, post-matching networks are usually added after the combing node, which usually occupy large circuit sizes. However, in this design, the post-matching network is not used. Instead, two ideal transformers and specific output matching components are employed at carrier and peaking branches. Then, by rearranging the output matching components in the two branches, Norton transformation can be used and the ideal transformers can be eliminated. In this way, the impedance at the combining node is directly matched to a 50- $\Omega $ load without using a post-matching network, resulting in both compact size and wide bandwidth. For verification, a broadband DPA prototype with a very simple structure is implemented. The fabricated circuit shows a compact size. A wide bandwidth from 1.3 to 2.8 GHz (73%) is achieved with a saturated output power of 41.4–44.6 dBm. The drain efficiencies at saturation and 6-dB back-off power level are 60.1–79.1% and 41.8–61%, respectively, which are comparable to those of state-of-the-art designs. [ABSTRACT FROM AUTHOR]

Injection-locked ring oscillators (ILROs) are widely used for quadrature clock generators (QCG) in multi-lane wireline or optical transceivers because of their low power, low area, and technology scalability. However, locking a four-stage I/Q oscillator with a two-phase injection signal generates imbalances in amplitude and phase, resulting in I/Q phase errors and degraded jitter performance. This paper proposes a modified frequency-domain analysis with amplitude constraint for even-phase ILROs. Combining theoretical derivations with simulation results in 28nm CMOS technology, the behaviors of ring oscillators with partial injection and ILRO-based QCG are discussed and concluded. [ABSTRACT FROM AUTHOR]

This paper presents a rigorous transfer function analysis of the power supply rejection ratio (PSRR) of low-dropout (LDO) regulators and the LDO with the feed-forward ripple cancellation (FFRC) scheme. Four main noise sources of conventional LDOs are first clarified. An efficient and accurate model is proposed to facilitate the analysis, and the transfer function, along with the poles and zeros, is derived based on the simplified model. Software simulation results and numerical plots are both demonstrated and compared to verify the analytical results, with respect to two specific design examples. The widely-used FFRC scheme for PSRR enhancement is also reinvestigated based on the proposed model. With the inclusion of the FFRC circuit, the new transfer function with new poles and zeros is presented. The working principles of the FFRC scheme are illustrated and the optimal FFRC case is clarified. The proposed model and the derived transfer function match well with the simulation results and the measurement results in prior works. The proposed model and the analytical results serve as the theoretical foundation of the design of high-PSRR LDOs. The recommended simulation methodology could be helpful during the circuit design phase. [ABSTRACT FROM AUTHOR]

To address some of the challenges of asynchronous design, we propose a new, decomposable asynchronous logic block architecture based on our TH $x2$ programmable threshold cell, and we use it to implement common threshold functions found in asynchronous, null convention logic circuits. At a minimum, programmable gate arrays require a programmable logic cell that can implement a complete set of logic. It is well known that a NAND function forms a complete set of logic, and in null convention logic, the TH12 and TH22 threshold cells are used to form a basic two-input NAND function. The TH $x2$ threshold cell is capable of performing both TH12 and TH22 operations, so it too forms a complete set of logic. In this paper, we present our eight-transistor mask-programmable gate array logic cell, 16-transistor field-programmable gate array logic cell, and new decomposable field-programmable gate array logic block architecture, all based on the TH $x2$ threshold cell and suitable for implementing null convention logic asynchronous functions. To minimize the TH $x2$ threshold cell area for both TH12 and TH22 modes, we designed a layout with common Euler paths and no diffusion breaks for both modes. The highly compact nature of the TH $x2$ threshold cell–along with the symmetry of the mask- and field-programmable gate array logic cells–made it an ideal candidate for an asynchronous field-programmable logic block structure. This paper is part of an ongoing project, and it only addresses the programmable logic block architecture, not a complete FPGA fabric. [ABSTRACT FROM AUTHOR]

This paper presents a fully differential wake-up receiver (WuRX) with ultra-low power and high sensitivity. Implementing the fully differential framework achieves differential signal processing without an off-chip balun, which achieves noise suppression and sensitivity improvement. The low voltage baseband signal processing (LVBSP) is proposed to cut down the power consumption, which is achieved by the low-voltage fast-response differential amplifier (LFDA) and the time-domain signal processing circuit. Moreover, the periodic offset cancellation technique (POCT) in the baseband circuit is proposed to alleviate the offset and low-frequency noise impacts. This WuRX is implemented in the TSMC 65-nm CMOS process occupying an active area of 0.18 mm2. When operating at 434 MHz, the proposed WuRX has a −75-dBm sensitivity at 250 bps while consuming 6.4 nW from 0.4 V supply voltage. [ABSTRACT FROM AUTHOR]

Coordinate Rotation Digital Computer (CORDIC) is a robust iterative algorithm that computes many transcendental mathematical functions. This paper proposes a reconfigurable CORDIC hardware design and FPGA realization that includes all possible configurations of the CORDIC algorithm. The proposed architecture is introduced in two approaches: multiplier-less and single multiplier approaches, each with its advantages. Compared to recent related works, the proposed implementation overpasses them in the included number of configurations. Additionally, it demonstrates efficient hardware utilization and suitability for potential applications. Furthermore, the proposed design is applied to a memristive chaotic system with different transcendental functions computed using the proposed reconfigurable block. The memristive system design is realized on the Artix-7 FPGA board, yielding throughputs of 0.4483 and 0.3972 Gbit/s for the two approaches of reconfigurable CORDIC. [ABSTRACT FROM AUTHOR]

In this paper, we describe a design of a mixed-signal circuit for an binary neuron (a.k.a perceptron, threshold logic gate) and a methodology for automatically embedding such cells in ASICs. The binary neuron, referred to as an FTL (flash threshold logic) uses floating gate or flash transistors whose threshold voltages serve as a proxy for the weights of the neuron. Algorithms for mapping the weights to the flash transistor threshold voltages are presented. The threshold voltages are determined to maximize both the robustness of the cell and its speed. The performance, power, and area of a single FTL cell are shown to be significantly smaller (79.4%), consume less power (61.6%), and operate faster (40.3%) compared to conventional CMOS logic equivalents. Also included are the architecture and the algorithms to program the flash devices of an FTL. The FTL cells are implemented as standard cells, and are designed to allow commercial synthesis and P&R tools to automatically use them in synthesis of ASICs. Substantial reductions in area and power without sacrificing performance are demonstrated on several ASIC benchmarks by the automatic embedding of FTL cells. The paper also demonstrates how FTL cells can be used for fixing timing errors after fabrication [ABSTRACT FROM AUTHOR]

This paper proposes a novel all-digital background calibration of timing mismatch for a time-interleaved analog-to-digital converter (TIADC). For two different calibration strategies, the absolute calibration and the relative calibration, the inductive expressions of modulation matrices are derived from the coefficient matrices provided by different estimation methods. Based on the modulation matrix, we develop a digital calibration architecture, which enables the output of TIADC to be modulated firstly before being corrected, so the costly matrix multiplication processing can be avoided. This calibration architecture also enables the estimation process of each channel to be independent and can be executed simultaneously, which accelerates the convergence speed of the timing mismatch. We show the efficiency of the calibration structure by simulations, including examples from the literature. Numerical simulation demonstrates that the convergence speed of the timing mismatch has been improved by at least 27%, compared with the estimation method depending on the specified reference channel. The result of FPGA-based hardware implementation shows that the spurious-free dynamic range (SFDR) is improved by 37.63dB. [ABSTRACT FROM AUTHOR]

The device faults commonly exist in microgrids (MGs) and often undermine the system stability. However, the existing distributed methods generally design control protocols based on the absence of faults or only considering actuator faults, which limits the applicability of controllers in MG systems. Therefore, this paper investigates an adaptive prescribed fixed-time performance (PFTP) consensus fault-tolerant control (FTC) problem for the voltage regulation of a nonlinear islanded MG inverter-based distributed generators (DGs) with output contactor and actuator fault via the state event-triggered mechanism. The PFTP method for the voltage restoration synchronization error is proposed by constructing a novel performance function to increase the speed of voltage recovery. Based on the estimation properties of fuzzy logic system, an unknown nonlinear function and the residual term of output contactor are estimated. Then, an adaptive state event-triggering mechanism is designed to reduce the communication burden, and its main advantage is that the control protocol is updated in the aperiodic way at the triggering instants. Further, according to backstepping technology, a novel adaptive event-triggered consensus FTC protocol is constructed to achieve the voltage regulation of islanded MG, and a parameter adaptive law is designed to compensate the adverse effects of the output contactor fault. Based on the Lyapunov stability theory, it is proved that the voltage recovery synchronization error satisfies the PFTP, and all signals in the closed-loop systems are cooperatively uniformly ultimately bounded. Finally, the proposed control strategy is also validated by using the MATLAB. [ABSTRACT FROM AUTHOR]

Information on the submission of papers for publication in the journal "IEEE Transactions on Circuit & Systems. Part I: Regular Papers" is presented.

This Special Issue of the IEEE Transactions on Circuits and Systems—I: Regular Papers (TCAS-I) includes papers presented at the International Symposium on Integrated Circuits and Systems (ISICAS) 2020. The third edition of ISICAS was held virtually on August 27–28, 2020. The Symposium welcomes high-quality original research papers in the areas of integrated circuits and systems, including but not limited to analog, digital, power, energy, biomedical, sensory, and communications systems. A reader will notice that all the papers presented in this Special Issue and at the conference describe integrated implementations in CMOS, hybrid, SiP, or SoC forms with experimental results—this is a mandatory requirement of the symposium. [ABSTRACT FROM AUTHOR]

The article presents information on how authors can submit papers or contributions to the journal "IEEE Transactions on Circuits & Systems: Regular Papers."

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

The article offers information on papers relevant to electronic circuits and systems that are accepted for publication in "IEEE Transactions on Circuits and Systems Part I: Regular Papers."

This paper studies the process scalability of pulse-mode CMOS circuits for analog 2-D convolution in computer vision systems. A simple, scalable architecture for an integrate and fire neuron is presented for implementing weighted addition of pulse-frequency modulated (PFM) signals. Sources of error are discussed and modeled in a detailed behavioral simulation and compared with equivalent transistor-level simulations. Next, the design of a 180-nm PFM chip with programmable weights is presented, and full image convolutions are demonstrated with the analog hardware. Preliminary chip measurements for a 45-nm implementation are also included to demonstrate process scalability. Design considerations for porting this architecture to nanometer processes, including FinFET technologies, are then discussed. This paper concludes with a simulation study on scaling down to 10 nm using a predictive technology model. [ABSTRACT FROM AUTHOR]

This paper addresses the issue of the optimal design of a grounded fractional order inductor using a generalized impedance converter. The nonidealities of the op amps have been taken into account while formulating the approximate frequency characteristics of the fractional order inductor for both Type-I and Type-II realizations. Based on these formulations a set of design guidelines is proposed to achieve minimum phase and magnitude errors for the realized fractional inductor. The minimization conditions have been validated by several simulation and experimental results. [ABSTRACT FROM AUTHOR]

In analog fault simulation, the number one challenge is that simulation time could grow rapidly and become prohibitive as the circuit size becomes large. This paper proposes a systematic method to significantly improve the time efficiency in estimating the fault coverage for analog fault simulation. In the proposed method, a circuit under test (CUT) is first partitioned into independent sub-circuits. This is accomplished through mapping the circuit into a graph, decomposing the graph into strongly connected components (SCCs), and generating a sub-circuit for each SCC. The impacts of potential faults directly entering a sub-circuit are then simulated and recorded using the sub-circuits, which is expected to be much more time efficient than fault simulation using the whole circuit, which is much larger in size. Finally, the fault detectability at the given test points is evaluated based on the fault impacts and sensitivity among different sub-circuits. As a first step toward quick estimation of fault coverage, this paper focuses on dc tests. Simulation results show that the fault coverage of dc tests can be estimated sufficiently accurately with simulation time being reduced by 10X for the benchmark circuit, or by approximately the number of SCCs. For a much larger circuit, the number of SCCs is expected to be much larger and the time-saving factor will be much larger. [ABSTRACT FROM PUBLISHER]

This paper is concerned with a method for design and analysis of specific neuronal networks, called central pattern generators (CPGs), which produce primary rhythmic patterns in animals. In particular, the paper is focused on synthetic CPGs made up of few basic elements and governing quadrupeds’ gaits and gait transitions, under the control of an external drive. The method combines the principles of bifurcation theory, geometric properties of symmetry, and numerical analysis based on the recently proposed toolbox CEPAGE. The method is applied to two CPGs, one bio-inspired and one purely synthetic. In both the cases, the method provides a way to obtain a desired sequence of gaits by continuously changing a bifurcation parameter related to the external drive. [ABSTRACT FROM AUTHOR]

This paper presents a family of algorithms based on sparse decompositions that detect anomalies in video sequences obtained from slow moving cameras. These algorithms start by computing the union of subspaces that best represents all the frames from a reference (anomaly free) video as a low-rank projection plus a sparse residue. Then, they perform a low-rank representation of a target (possibly anomalous) video by taking advantage of both the union of subspaces and the sparse residue computed from the reference video. Such algorithms provide good detection results while at the same time obviating the need for previous video synchronization. However, this is obtained at the cost of a large computational complexity, which hinders their applicability. Another contribution of this paper approaches this problem by using intrinsic properties of the obtained data representation in order to restrict the search space to the most relevant subspaces, providing computational complexity gains of up to two orders of magnitude. The developed algorithms are shown to cope well with videos acquired in challenging scenarios, as verified by the analysis of 59 videos from the VDAO database that comprises videos with abandoned objects in a cluttered industrial scenario. [ABSTRACT FROM AUTHOR]

Inadvertent but inevitable mismatches among nominally identical unit element 1-bit digital-to-analog converters (DACs) within a multi-bit Nyquist-rate DAC cause both static and dynamic error in the DAC’s continuous-time output waveform. Prior calibration techniques are able to suppress static mismatch error, but have had limited success in suppressing dynamic mismatch error. This paper presents a digital calibration technique that adaptively measures and cancels both static and dynamic mismatch error over the DAC’s first Nyquist band. The technique is capable of either foreground or background operation, and is relatively insensitive to non-ideal circuit behavior. The paper presents a rigorous mathematical analysis of the technique, and demonstrates the results of the paper with both behavioral and transistor-level circuit simulations. [ABSTRACT FROM PUBLISHER]

Impedance transformation is one of the central concepts in high-frequency circuits and systems and is used ubiquitously for optimal power matching, noise matching, and high-efficiency power delivery to the antenna by power amplifiers. The matching network can be generally expressed as a path on the Smith chart and given the load and source impedances, there are theoretically infinite ways to achieve the transformation. When losses are included, each path will encounter a different loss, and currently, no comprehensive theory exist for finding the most optimal matching network. Furthermore, the networks will also provide different bandwidths of operation. Due to the matching network losses, it is often not optimal to force conjugate matching for maximizing end-to-end power transfer efficiency. In this paper, we provide a method toward finding 1) the globally most efficient path between two arbitrary impedances with lossy passives; 2) given the source and the load impedances, the optimal (typically non-conjugate) impedance to match and the highest efficiency path to reach the impedance; and 3) upper bounds on achievable efficiencies under the various scenarios. This paper also proposes ways to combine this method with nonlinear load-pull simulations for optimal combiner and matching network for integrated power amplifiers. This analysis creates interesting ways to maximize efficiency and bandwidths simultaneously and the paper also discusses this joint optimization. To the best of our knowledge, this is the first comprehensive analysis of globally optimal impedance transformation networks between arbitrary impedances with lossy passives. [ABSTRACT FROM PUBLISHER]

This paper proposes to utilize intentional time delays as part of controllers to improve the damping of electromechanical oscillations of power systems. Through stability theory, the control parameter settings for which these delays in Power System Stabilizers (PSSs) improve the small signal stability of a power system are systematically identified, including the key parameter settings for which stability regions in the parameter plane remain connected for effective operation. The paper shows that PSSs with two control channels can be effectively designed to achieve best damping characteristics for a wide range of delays. Analytical results are presented on the One-Machine Infinite-Bus (OMIB) electromechanical power system model. To demonstrate the opportunities in more realistic dynamic models, our results are then implemented via numerical analysis on the IEEE standard 14-bus system. [ABSTRACT FROM AUTHOR]

When applied to artificial intelligence edge devices, the conventionally von Neumann computing architecture imposes numerous challenges (e.g., improving the energy efficiency), due to the memory-wall bottleneck involving the frequent movement of data between the memory and the processing elements (PE). Computing-in-memory (CIM) is a promising candidate approach to breaking through this so-called memory wall bottleneck. SRAM cells provide unlimited endurance and compatibility with state-of-the-art logic processes. This paper outlines the background, trends, and challenges involved in the further development of SRAM-CIM macros. This paper also reviews recent silicon-verified SRAM-CIM macros designed for logic and multiplication-accumulation (MAC) operations. [ABSTRACT FROM AUTHOR]

As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe issues as jitters below 10 fs are sought. The results are also applied to the sampling clocks in analog-to-digital converters and suggest that clock generation may consume a greater power than the converter itself. [ABSTRACT FROM AUTHOR]

The series-paralleling technique of dc-dc converters is utilized in various domains of electrical engineering for improved power conversion. Previous studies have proposed and classified the control schemes for the series-paralleled converters. However, they have several restrictions and lack diversity. The purpose of this paper is to propose passivity-based control (PBC) for the diverse output series-parallel connection of dc-dc converters. It is proved that the output series-paralleled converters regulated by PBC are asymptotically stable. The output series-paralleled converters are numerically simulated to confirm the asymptotic stability. PBC is shown to maintain the stability of the output series-paralleled converters with diverse circuit topologies, parameters, and steady-states. The result of this paper theoretically supports the numerical and experimental considerations in the previous studies and justifies the further extension of the series-parallel connection. [ABSTRACT FROM AUTHOR]