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This paper presents a digital battery management unit (BMU) with built-in resistance (BIR) compensation, modulated frequency detection (MFD), and multi-mode protection (MMP) techniques to realize fast, efficient and safe charging. The charger incorporates the proposed BMU based on the low-dropout (LDO) regulator. With BIR compensation, a large rated current in the proposed pulsed constant current (PCC) mode charges the battery, and reduces the charging time by omitting the constant-voltage (CV) mode. The MFD technique allows continuous monitoring and obtains precise BIR compensation with accelerating sampling speed. The MMP technique can alleviate safety concerns while charging, including over-voltage protection (OVP), over-current protection (OCP), and the proposed accidental fluctuation protection (AFP). The digital BMU, implemented in 28 nm CMOS, occupies 0.014 mm2 of silicon area. Experimental results show that the proposed circuit saves 73.3% of charging time with 1.5A charging current, and 21.5% ADC dynamic power with 1A charging current. For the digital controller IC, the power consumption is $59.1~\mu \text{W}$. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

This index covers all technical items - papers, correspondence, reviews, etc. - that appeared in this periodical during the year, and items from previous years that were commented upon or corrected in this year. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the co-authors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index. [ABSTRACT FROM PUBLISHER]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM AUTHOR]

Clock skew and component mismatches in continuous-time DACs introduce two types of error: static error and dynamic error. Both types of error typically limit the performance of practical, high-resolution, and continuous-time DACs, but most prior calibration techniques primarily reduce only static error. An exception is a recently published mismatch noise cancellation (MNC) technique that adaptively measures and cancels both types of error over the DAC’s first Nyquist band. However, a disadvantage of the technique is that it requires an oversampling ADC that operates at several times the DAC’s Nyquist rate to prevent convergence error that would otherwise be caused by aliasing. This paper presents a sub-sampling version of the MNC technique that avoids this limitation at the expense of a lower calibration convergence rate. As proven in the paper, the subsampling MNC technique allows aliasing to occur, but in such a way that convergence error is avoided. [ABSTRACT FROM AUTHOR]

The integral nonlinearity of digital-to-analog converters manifests itself as adjacent-channel power in RF transmitters. This paper derives compact equations relating these two quantities and verifies the results by simulations. Both current-steering and switched-mode architectures are analyzed. [ABSTRACT FROM AUTHOR]

In this paper, a novel saturation-based control method is proposed for high-order sliding mode (HOSM) dynamics with upper-triangular nonlinearities. Firstly, a new HOSM dynamics with upper-triangular nonlinearities is constructed based on the traditional HOSM dynamics, so as to reduce the uncertainties in the control input channel. Then, a HOSM controller is established by means of the adding a power integrator method such that the new HOSM dynamics is locally stabilized. Finally, the saturation-based controller is constructed by a combination of the saturation technique and the local HOSM controller to guarantee that the sliding variables can converge into a domain of attraction in a finite time and retain inside it thereafter. The rigorous stability analysis is made by the Lyapunov theory. A simulation example is also given to demonstrate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Information on the submission of papers for publication in the journal "IEEE Transactions on Circuit & Systems. Part I: Regular Papers" is presented.

This Special Issue of the IEEE Transactions on Circuits and Systems—I: Regular Papers (TCAS-I) includes papers presented at the International Symposium on Integrated Circuits and Systems (ISICAS) 2020. The third edition of ISICAS was held virtually on August 27–28, 2020. The Symposium welcomes high-quality original research papers in the areas of integrated circuits and systems, including but not limited to analog, digital, power, energy, biomedical, sensory, and communications systems. A reader will notice that all the papers presented in this Special Issue and at the conference describe integrated implementations in CMOS, hybrid, SiP, or SoC forms with experimental results—this is a mandatory requirement of the symposium. [ABSTRACT FROM AUTHOR]

This special issue of the IEEE Transactions on Circuits and Systems - Part I: Regular Papers (TCAS-I) includes papers presented at the International Symposium on Integrated Circuits and Systems (ISICAS) 2019. The second edition of ISICAS was held on 29–30 August 2019 in Venice, Italy. The Symposium welcomes high-quality original research papers in the areas of integrated circuits and systems, including but not limited to analog, digital, power, energy, biomedical, sensory and communications systems. The reader will notice that all the papers presented in this special issue and at the conference describe integrated implementations in CMOS, hybrid, SiP or SoC forms with experimental results – this is a mandatory requirement of the Symposium. [ABSTRACT FROM AUTHOR]

The article offers information for authors submitting manuscripts to the journal "IEEE Transactions on Circuits and Systems Part I: Regular Papers."

The article provides information on the journal "IEEE Transactions on Circuits and Systems I: Regular Papers."

The article provides information on the journal "IEEE Transactions on Circuits and Systems I: Regular Papers."

This paper proposes a new design methodology to explore the state-of-the-art approximate adders for accelerator architectures conceived in the realm of multiplier-less multiple constant multiplication optimization problem. The proposed methodology is composed of: 1) a search heuristic to seek faster and feasible approximate configurations for the architectures under evaluation; 2) low-power techniques regarding hybrid approximate adders design for accelerators based on trees of shift-and-add operations; 3) high-performance evaluation by exploring parallel prefix adders and low power analysis through the use of the adder optimized by a commercial synthesis tool in the precise part of the approximate adders; and 4) energy efficiency analysis by considering both the approximate techniques and voltage over scaling estimation. Furthermore, improvements are proposed for the state-of-the-art approximate adders under evaluation in this paper. Two case studies are considered to assess the proposed methodology: 1) Gaussian image filter and 2) Sobel operator. The precise and approximate image filters were described in very high-speed integrated circuits hardware description language regarding the proposed methodology. Results are shown after synthesis to a 45-nm standard cell-based technology, where energy reductions ranging from 7.7% up to 73.2% were experienced for multiple levels of quality considering the applications under analysis. [ABSTRACT FROM AUTHOR]

This paper describes a low voltage physically unclonable function (PUF) implemented with SRAM circuits. The approach allows the use of foundry cells, which are used in this paper, and requires very minor modifications to standard SRAM arrays. The PUF functionality is designed into large 1M-bit SRAM arrays fabricated on a 55-nm process using the foundry supplied SRAM cell layouts. The low variability foundry process produces good PUF results, demonstrating that the approach should also be good on conventional processes, since greater mismatch should positively impact PUF performance as measured by code word stability. The impact of process corners is also experimentally determined. Unstable bits, which we attribute to random telegraph noise is shown to be at manageable levels. We describe the circuit operation, statistical behavior, and suggest helper data functions that allow operation without error correction. This is important since error correction necessarily allows some leakage of the underlying secret codes. [ABSTRACT FROM AUTHOR]

The article offers information for authors submitting manuscripts to the "IEEE Transactions on Circuits and Systems-- I: Regular Papers."

This paper investigates the exponential synchronization (ES) problem for complex networks (CNs) under an intermittent adaptive event-triggered control (IAE-TC) strategy which is based on dynamic IAE-TC during the control activation intervals. In this control mechanism, the intermittent controller has adaptability to the evolution results of the controlled networks and is activated only when the event-triggered condition is violated. Then, by employing this kind of control strategy and the Lyapunov method, some sufficient conditions are proposed to achieve the ES of CNs and it is proven that the Zeno behavior can be eliminated. Besides, an application about the islanded microgrid system and some numerical simulations are provided to verify the effectiveness of the derived theoretical results. Moreover, in the numerical simulations, it is shown that the dynamic IAE-TC strategy can decrease the number of event-triggered instants more availably than the static one. [ABSTRACT FROM AUTHOR]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM PUBLISHER]

This paper considers a large class of memristor circuits of arbitrary order, and containing an arbitrary number of flux- or charge-controlled memristors, for which a state equation (SE) description can be obtained. By means of the SEs, it is shown that the state space of each circuit can be decomposed in infinitely many manifolds, and that in the autonomous case, each manifold is positively invariant and is characterized by a different reduced-order dynamics and attractors. These results are the basis for extending the analysis to the non-autonomous case, where time-varying independent sources are present. In particular, the chief result obtained in this paper shows how to analytically design external pulses for programming memristor circuits, i.e., how invariant manifolds and attractors can be changed and controlled by applying suitable charge or flux sources via time-varying voltage and/or current pulses with finite time duration. The main results are obtained by relying on a recently introduced technique for the analysis of memristor circuits in the flux-charge domain. [ABSTRACT FROM AUTHOR]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM PUBLISHER]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM PUBLISHER]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM PUBLISHER]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM AUTHOR]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM AUTHOR]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM PUBLISHER]

The article presents guidelines on how researchers can publish their studies on integrated circuits and systems in the future issues of "IEEE Transactions on Circuits and Systems."

The article presents guidelines on how researchers can publish their studies about integrated circuits and systems in the future issues of "IEEE Transactions on Circuits and Systems."

This paper investigates the formation control problem for a group of nonholonomic mobile robots (NMRs) with unknown parameters and deception attacks. The information transmitted among different robots is represented by a directed graph and only a subset of the robots can obtain the full information of the desired trajectory directly. For those robots which cannot access to the reference trajectory directly, distributed estimators are designed to estimate the unknown trajectory information by using only locally available information. Besides, the sensor-to-controller transmitting channels and the communication among connected robots are suffering from deception attacks. Adaptive laws and compensation terms are designed to handle the issue of attack-induced uncertainties. Then, a novel distributed resilient formation control scheme is designed, based on which a sufficient condition is developed to guarantee that the formation errors converge to a compact set and all the closed-loop signals are bounded. Experimental results are given to validate the theoretical studies. [ABSTRACT FROM AUTHOR]

Silicon-based terahertz (THz) integrated circuits (ICs) have made rapid progress over the past decade. The demonstrated basic component performance, as well as the maturity of design tools and methodologies, have made it possible to build high-complexity THz integrated systems. Such implementations are undoubtedly highly attractive due to their low cost and high integration capability; however, their unique characteristics, both advantageous and disadvantageous, also call for research investigations into unconventional systematic architectures and novel THz applications. In this paper, we review the current status and future trend of silicon-based THz ICs, with the focus on state-of-the-art THz microsystems for emerging sensing and communication applications in the last few years, such as high-resolution imaging, high medium/long-term stability time keeping, high-speed wireline/wireless communications, and miniaturization of RF tags, as well as THz packaging technologies. [ABSTRACT FROM AUTHOR]

Diffusion-driven instabilities with pattern formation may occur in a network of identical, regularly-spaced, and resistively-coupled cells if and only if the uncoupled cell is poised on a locally-active and stable operating point in the Edge of Chaos domain. This manuscript presents the simplest ever-reported two-cell neural network, combining together only 7 two-terminal components, namely 2 batteries, 3 resistors, and 2 volatile NbOx memristive threshold switches from NaMLab, and subject to diffusion-driven instabilities with the concurrent emergence of Turing patterns. Very remarkably, this is the first time an homogeneous cellular medium, with no other dynamic element than 2 locally-active memristors, hence the attribute all-memristor coined to address it in this paper, is found to support complex phenomena. The destabilization of the homogeneous solution occurs in this second-order two-cell array if and only if the uncoupled cell circuit parameters are chosen from the Edge of Chaos domain. A deep circuit- and system-theoretic investigation, including linearization analysis and phase portrait investigation, provides a comprehensive picture for the local and global dynamics of the bio-inspired network, revealing how a theory-assisted approach may guide circuit design with inherently non-linear memristive devices. [ABSTRACT FROM AUTHOR]

An automatic inductor design process is helpful to reduce the design cycle of radio frequency (RF) integrated circuit (IC). This paper proposed an efficient synthesis-analysis machine (SAM) for on-chip inductor synthesis and modeling, as well as an automatic dataset generation (ADG) topology for the generation of artificial neural networks (ANNs) training dataset. The SAM consists of a synthesis ANN, two analysis ANNs and a proposed self-inspection machine (SIM). For a given design request, the SAM synthesizes a layout first, followed by analyzing the performance of the layout automatically, and finally improves the layout confidence through self-inspection. Compared to the modeling functions of analysis ANN, the synthesis ANN behaves as an inverse model, of which the inputs are desired inductor performances while the outputs are geometrical parameters of the layout. However, multi-value problems might occur in obtaining geometries of inductors, suggesting with evidence from mathematic relationships between geometrical and electrical parameters of an inductor. A multi-valued training dataset will mislead the synthesis ANN, resulting in unqualified layouts. To deal with this issue, a solution space contraction technique (SSCM) is also proposed. Furthermore, the SIM suspends most of the failures by comparing the output of analysis ANN back to the input of synthesis ANN. An electromagnetic simulation tool is used for experiments, and the effectiveness of the proposed SAM is proven by 6,500 inductor samples. [ABSTRACT FROM AUTHOR]

Recent studies on integrated circuits interconnections are mainly concentrated on the analysis of crosstalk and delay, by taking the trade-off between accuracy, speed, and complexity into consideration. The new idea of this paper is to apply the convex optimization method to analyze crosstalk and delay of the lossy coupled interconnections in identical and non-identical forms. For this purpose, a simple and comprehensive model is proposed to cover the functional and dynamic crosstalk in a computationally-effective way. More specifically, various case studies are determined to analyze the transient response of the coupled transmission lines with arbitrary excitation sources in the presence of both capacitive and inductive coupling characteristics. To validate the model, the numerical and Advanced Design System (ADS) simulation results are compared to indicate the desired accuracy. The calculated crosstalk percentage error of the proposed model with respect to ADS and HSPICE are less than 1.03% and 1.19%, respectively. In addition, the computational speed of the proposed method is about twice higher than ADS and HSPICE. The proposed model is extendible to handle ${N}$ coupled lines, making it appropriate to model complex integrated circuit interconnections. [ABSTRACT FROM AUTHOR]

This paper introduces a tunable fractional order parallel resonator (FOPR) whose resonating frequency can be tuned by the coefficient of a fractional order (FO) element (fractor). At the same time, its $Q$- factor can be set very high (theoretically infinite) by varying its resistor. Using this FOPR circuit, two simple FO filters (FO bandpass and FO notch) are also developed. The paper includes detail sensitivity analyses of these circuits for various circuit parameters and describes how different design parameters of proposed FOPR and FO filters are chosen accordingly. Proposed FOPR and FO filters are simulated in MATLAB and realized in hardware. The hardware circuits are tested practically, and detail experimental results are provided. It is found that the experimental data are in good agreement with the simulation data. In hardware, the realized FOPR has achieved a Q$-factor up to 360, and the realized FO notch filter has {Q}>10 when its attenuation is more than 30 dB. Different practical aspects of filter tuning are also described in detail. [ABSTRACT FROM PUBLISHER]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM PUBLISHER]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM PUBLISHER]

The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions. However, while recent voltage references can meet most of these requirements with a handful of transistors, current references remain rather complex, requiring significant design time and silicon area. In this paper, we present a family of simple current references consisting of a two-transistor (2T) ultra-low-power voltage reference, buffered onto a voltage-to-current converter by a single transistor. Two topologies are fabricated in a 0.18- $\mu \text{m}$ partially-depleted silicon-on-insulator (SOI) technology and measured over 10 dies. First, a 7T nA-range proportional-to-absolute-temperature (PTAT) reference intended for constant- $g_{m}$ biasing of subthreshold operational amplifiers demonstrates a 0.096-nA current with a line sensitivity (LS) of 1.48 %/V, a temperature coefficient (TC) of 0.75 %/°C, and a variability $(\sigma /\mu)$ of 1.66 %. Then, two 4T+1R $\mu \text{A}$ -range constant-with-temperature (CWT) references with (resp. without) TC calibration exhibit a 1.09- $\mu \text{A}$ (resp. 0.99- $\mu \text{A}$) current with a 0.21-%/V (resp. 0.20-%/V) LS, a 38-ppm/°C (resp. 290-ppm/°C) TC, and a 0.87-% (resp. 0.65-%) $(\sigma /\mu)$. In addition, portability to common scaled CMOS technologies, such as 65-nm bulk and 28-nm fully-depleted SOI, is discussed and validated through post-layout simulations. [ABSTRACT FROM AUTHOR]

This paper develops fundamental limits of digital phased arrays and proposes to use this as a map for the future technology investment in this area. Phased arrays, which are becoming ubiquitous in everything from vehicles, to communication systems including cell phones, to drones, satellites, and of course military applications. There is a recent trend toward digital phased arrays where each element in the antenna array is digitized. This allows monolithic integrated circuit integration as well as providing new capability due to digital signal processing. Digital phased arrays are increasingly being implemented with reconfigurable logic. Digitization and reconfigurability comes at a cost of power, which is increasingly becoming the limitation in these systems. This paper develops the fundamental energy limits of digital computation, applies this to phased arrays, and discusses directions for potential future digital phased array development. [ABSTRACT FROM AUTHOR]

The emerging area of network science and engineering is concerned with the study of structural characteristics of networks, their impact on the dynamical behavior of systems as revealed through their topological properties, random evolution of networks, information spreading along a network, and so on. This area spans a wide range of applications in different disciplines. A topic of great interest in this area is the notion of network criticality. Most measures of network criticality are defined by the paths that flow through the nodes or edges. Since computing all the paths is computationally intractable, only the shortest paths are usually used for computing criticality metrics. Thus, measures that implicitly capture the impact of all the paths will be useful. The recently introduced concepts of the resistance distance and the Kirchhoff Index are two such measures. In this paper, we study these metrics and present several results that extend, generalize, and unify earlier works reported in the literature. In developing these results, the role of circuit theoretic concepts is emphasized. We also relate our works to Foster’s theorems and present a generalization that captures and retains the circuit theoretic elegance of Foster’s original theorems. [ABSTRACT FROM AUTHOR]

This paper identifies novel directions of standard-cell-based synthesizable memory design. A compact 18T-bitcell of OR-AND-Invert (OAI) and AND-OR-Invert (AOI) logic gates is presented with bit-selective write and multiplexed read accesses. It reduces the bitcell area by 11%–40% compared to the state-of-the-art clock-gating-based D-latch schemes while avoiding custom-cell design. The improved storage density comes from the tight integration on two levels–coupling the read multiplexing within each bitcell and taking advantage of structured datapath placement in bitcell arrays by using commercial CAD tools. As measured on a 40 nm SRAM of 90 kb, the OAI/AOI-gate-based synthesizable memory features 0.4 V minimum access voltage, 30 fJ minimum read energy per bit, and a leakage power of 1.4 pW per bit at 0.3 V data retention voltage. It is ideally suited for IoT-node design operating in sub- $V_{\mathrm {t}}$ for joint dynamic energy and leakage power reduction. Further, it enables fast turn-around times by IP reuse over technology nodes with minimal (re)design effort. [ABSTRACT FROM AUTHOR]

Although the multiband-structured subband adaptive filter (MSAF) and its convergence analysis have been widely studied, the existing analyses are carried out only in the decimated time domain. In this paper, we present a new theoretical mean-square analysis of the multi-sampled MSAF (MS-MSAF) algorithm in the original time domain, whereas the MS-MSAF algorithm extends the original sub-sampled number to a general value. Both the transient and steady-state performances are investigated, which provides a guideline for increasing the convergence rate of the MSAF. Then, the tracking ability is studied in a non-stationary environment. Moreover, the approximative analytical minimum mean-square deviation and optimum step size are derived. Simulation results illustrate the derived performance expressions, which show that there is a relatively good match between theory and practice. [ABSTRACT FROM AUTHOR]

This paper presents a fifth-order continuous-time Gm-C-based quadrature bandpass sigma-delta ($\Delta \Sigma$) modulator for Internet-of-Things applications. In the presented $\Delta \Sigma $ modulator, a reconfigurable full-scale input amplitude assists the $\Delta \Sigma $ modulator, achieving a wide dynamic range (DR) and a low-noise floor. A following system-level supply voltage and temperature background tracking technique stabilizes the frequency response of the Gm-C-based quadrature bandpass $\Delta \Sigma $ modulator. Furthermore, the 1.5-bit feedback current DAC employs a PN-based semi-self-swapping logic to relax the matching requirement. The prototype $\Delta \Sigma $ modulator was fabricated in a 180-nm CMOS process with an active area of 0.28 mm2. The $\Delta \Sigma $ modulator achieves a total DR of 93.7 dB with the reconfigurable full-scale input amplitude, resulting in a noise spectral density of −153.7 dBFS/Hz with a bandwidth of 1 MHz. The presented $\Delta \Sigma $ modulator consumes 2.0 mW with a power supply of 1.8 V and a sampling frequency of 32 MHz. [ABSTRACT FROM AUTHOR]

This paper presents a 24-channel time-shared 8-bit digital-to-analog converter (DAC) with dual sampling to minimize the effective channel area of the column driver integrated circuit (IC) for high-resolution active-matrix organic light emitting diodes (AMOLED). The proposed time-shared DAC significantly reduces the effective channel area of the column driver IC, since a single high-speed DAC is shared among multi channels. The dual-sampling architecture for the output amplifiers also reduces the power consumption of the column driver IC, where the operating time of the time-shared DAC and the output amplifier is efficiently handled during the limited 1-horizontal time. The sampling accuracy of the dual-sampling architecture is improved by a simple dummy switch and a source follower. The proposed time-shared DAC with the dual sampling is implemented by a 0.13- $\mu \text{m}$ high-voltage complementary metal-oxide-semiconductor process and integrated in a 960-channel column driver IC, while the effective channel area of the column driver IC is 5520 $\mu \text{m}^{2}$. As a result of driving an 11-inch-wide quad extended graphics array AMOLED panel by using the prototype column driver IC, the panel uniformly generates a clear image. [ABSTRACT FROM AUTHOR]

The twelve papers in this special section were presented at the 2013 IEEE Custom Integrated Circuits Conference (CICC 2013)that was held in San Jose, CA, September 2013. [ABSTRACT FROM AUTHOR]

This paper presents a systematic procedure that can be used to create operational transconductance amplifiers (OTAs) for closed-loop operation using multiple low-gain stages to realize extremely high DC gain. Such devices are necessary to realize analog functions with demanding absolute accuracy requirements, e.g., high-resolution ADCs and DACs. The principle is based on the cascade of undamped integrators to realize large DC gains and a state-space derived controller to stabilize its operation in a closed-loop configuration. A programmable OTA fabricated in the IBM 130 nm CMOS process is used as a test vehicle to prove the design principle through its 2 to 5th-order realization. Measured data reveals DC gains ranging from 50 to 150 dB with a 3-dB bandwidth of 10 kHz and a unity gain frequency of 10 MHz. While this paper demonstrates the design principles using CMOS integrated circuits, the principle is general and can be applied to any type of circuit technology in integrated or discrete implementation. Moreover, the methods are easily automated as the principles are based on closed-form formulae as opposed to iterative numerical search techniques. [ABSTRACT FROM PUBLISHER]

A 400 Mb/s∼2.5 Gb/s referenceless clock and data recovery (CDR) IC is presented. This paper shows that the half-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability in itself. By using this intrinsic frequency detection capability of the half-rate linear PD, a CDR can be implemented in the single loop architecture without both an external reference clock and a separate frequency detector. For verification, a prototype CDR IC was fabricated in a 0.13 \mu\textm CMOS process. With 2.5 Gb/s, 2^31 - 1 pseudorandom binary sequence (PRBS), the measurement results show that the frequency acquisition time is 17 \mu\texts, the bit error rate (BER) is better than 10−12, the jitter of the recovered clock is 8.6 \textps\mathrm{rms} and the out-of-band jitter tolerance is 0.32 \textUI\mathrm{pp}. [ABSTRACT FROM PUBLISHER]

This paper presents a hybrid precoding processor for millimeter wave (mmWave) multiple-input-multiple-output (MIMO) communication systems. The proposed architecture supports 64 antennas with 4-to-8 RF chains, and 4-bit phase resolution for each phase shifter in the analog beamformer. A polar decomposition (PD) engine is designed to achieve a 2.4-to- $8.6\times $ lower latency with 1.5-to- $1.7\times $ less normalized gate count compared to the singular value decomposition (SVD)-based implementation for the same functionality. Multiplicands are combined to reduce 55% area by utilizing the distributive property. Approximate phase extraction and low-precision multiplication for quantized phase extraction are adopted, which leads to 43% and 41% area reductions, respectively. The proposed hybrid precoding processor is designed in a 40-nm CMOS technology. It delivers a throughput of up to 10,288 kMat/s and consumes 170.9 mW at 278 MHz. It outperforms the state-of-the-art hybrid precoding processors with 5.5- $13.7\times $ higher normalized area efficiency and 6.9- $38.4\times $ lower normalized energy. [ABSTRACT FROM AUTHOR]

The paper introduces a new concept of a true random number generator (TRNG). Most metastability-based solutions operate on the uncertainty of a logical output state of a device (flip-flop, D-latch) aimed to be resolved from an exact metastable point. However, it has been shown that the metastable point of a bistable circuit (which is practically impossible to reach) does not guarantee absolute randomness or sufficient entropy. We propose the concept of a device in which the direct proximity of the metastable point is not mandatory. In our concept the transition times of two devices are compared. Such construction is less sensitive to the proximity of the metastable point, temperature fluctuations, and power supply instabilities. The paper briefly describes the metastability phenomena in general and other known metastability-based TRNG concepts. A new concept of a dual-metastability time-competitive generator is presented, analyzed both numerically and theoretically, and verified based on the sample circuit's implementation. Empirical and statistical test results are presented. [ABSTRACT FROM AUTHOR]

The eleven papers in this special section were presented at the Custom Integrated Circuits Conference, held in San Jose, CA, in September 2011. The papers are grouped into three broad areas?analog,digital/memory, and RF circuits. [ABSTRACT FROM PUBLISHER]

This paper presents a 3.125-to-28.125 Gb/s dual-lane multi-standard parallel transceiver supporting channel-independent operation. Network equipment supports multiple data rates to encompass diversified communication standards. However, network equipment supports only a fixed number of channels at each supported data rate. This lack of flexibility limits the utilization rate of the network equipment. This study proposes a clock and data recovery (CDR) IC to obtain utilization flexibility and scalability in each channel with complete channel independency. The CDR IC achieves a wide tuning capability for data rates ranging from 3.125 to 28.125 Gb/s with low clock jitter owing to the use of injection-locked oscillators in each channel. Each CDR lane generates a channel-independent injection clock signal with a fixed-frequency global clock signal using a variable clock divider and a phase rotator with the proposed harmonic distortion compensator. In addition, a frequency tracking loop is proposed using a bang-bang phase detector-based natural frequency detector to align the natural frequency of the injection-locked oscillator with the input data rate, thereby suppressing the injection spur. The test chip fabricated in a 40 nm CMOS exhibits a power efficiency of 4.72 mW/Gb/s, while generating a recovered clock jitter of 976 fsrms at a data rate of 25.78125 Gb/s. [ABSTRACT FROM AUTHOR]

This paper presents an IC that extends the voltage capability of a low voltage battery charger to 100V for accurately and reliably charging lithium ion (Li-Ion) battery stacks of up to 18 cells. The IC interfaces with a buck converter battery charger that utilizes external nFET control and an external inductor current sensing resistor. The voltage extender IC provides voltage level translation for the nFET control signals and the current sensing function while supporting an input power supply voltage of up to 100V and output battery voltage of up to 80V. The inductor current sense voltage is translated with a ping-pong amplifier capable of driving a bi-directional input voltage to a fully differential output with a maximum load current of 10 mA at 20 MHz bandwidth and less than $500~\mu \text{V}$ offset. The combined system of the voltage extender IC and battery charger achieved 97% efficiency at a 4-A charging current. The battery charging voltage accuracy was better than ± 0.5% at 80V. [ABSTRACT FROM AUTHOR]