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The design of a 13.56 MHz/402 MHz autonomous wireless sensor node with asynchronous ECG monitoring for near field communication is presented. The sensor node consists of an RF energy harvester (RFEH), a power management unit, an ECG readout, a data encoder and an RF backscattering transmitter. The energy harvester supplies the system with 1.25 V and offers a power conversion efficiency of 19% from a ${-}13$ dBm RF source at 13.56 MHz. The power management unit regulates the output voltage of the RFEH to supply the ECG readout with ${\rm V}_{\rm ECG} = 0.95$ V and the data encoder with ${\rm V}_{\rm DE} = 0.65$ V . The ECG readout comprises an analog front-end (low noise amplifier and programmable voltage to current converter) and an asynchronous level crossing ADC with 8 bits resolution. The ADC output is encoded by a pulse generator that drives a backscattering transmitter at 402 MHz. The total power consumption of the sensor node circuitry is 9.7 $\mu$ W for a data rate of 90 kb/s and a heart rate of 70 bpm. The chip has been designed in a 0.18 $\mu$ m CMOS process and shows superior RF input power sensitivity and lower power consumption when compared to previous works.

A continuous-time level-crossing analog-to-digital converter (LC-ADC) for biomedical applications is presented. When compared to uniform-sampling (US) ADCs LC-ADCs generate fewer samples for various sparse biomedical signals. Lower power consumption and reduced design complexity with respect to conventional LC-ADCs are achieved due to: 1) replacing the n-bit digital-to-analog converter (DAC) with a 1-bit DAC; 2) splitting the level-crossing detections; and 3) fixing the comparison window. Designed and implemented in 0.18 μm CMOS technology, the proposed ADC uses a chip area of 220 × 203 μm(2). Operating from a supply voltage of 0.8 V, the ADC consumes 313-582 nW from 5 Hz to 5 kHz and achieves an ENOB up to 7.9 bits.

An ECG recording front-end with a continuous- time asynchronous level-crossing analog-to-digital converter (LC-ADC) is proposed. The system is a voltage and current mixed-mode system, which comprises a low noise amplifier (LNA), a programmable voltage-to-current converter (PVCC) as a programmable gain amplifier (PGA) and an LC-ADC with calibration DACs and an RC oscillator. The LNA shows an input referred noise of 3.77 μVrms over 0.06 Hz-950 Hz bandwidth. The total harmonic distortion (THD) of the LNA is 0.15% for a 10 mVPP input. The ECG front-end consumes 8.49 μW from a 1 V supply and achieves an ENOB up to 8 bits. The core area of the proposed front-end is 690 ×710 μm2, fabricated in a 0.18 μm CMOS technology.