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Associative memory is a cornerstone of cognitive intelligence within the human brain. The Bayesian confidence propagation neural network (BCPNN), a cortex-inspired model with high biological plausibility, has proven effective in emulating high-level cognitive functions like associative memory. However, the current approach using GPUs to simulate BCPNN-based associative memory tasks encounters challenges in latency and power efficiency as the model size scales. This work proposes a scalable multi-FPGA high performance computing (HPC) architecture designed for the associative memory system. The architecture integrates a set of hypercolumn unit (HCU) computing cores for intra-board online learning and inference, along with a spike-based synchronization scheme for inter-board communication among multiple FPGAs. Several design strategies, including population-based model mapping, packet-based spike synchronization, and cluster-based timing optimization, are presented to facilitate the multi-FPGA implementation. The architecture is implemented and validated on two Xilinx Alveo U50 FPGA cards, achieving a maximum model size of 200×10 and a peak working frequency of 220 MHz for the associative memory system. Both the memory-bounded spatial scalability and compute-bounded temporal scalability of the architecture are evaluated and optimized, achieving a maximum scale-latency ratio (SLR) of 268.82 for the two-FPGA implementation. Compared to a two-GPU counterpart, the two-FPGA approach demonstrates a maximum latency reduction of 51.72× and a power reduction exceeding 5.28× under the same network configuration. Compared with the state-of-the-art works, the two-FPGA implementation exhibits a high pattern storage capacity for the associative memory task.

Non-invasive, closed-loop brain modulation offers an accessible and cost-effective means of evaluating and modulating one's mental and physical well-being, such as Parkinson's disease, epilepsy, and sleep disorders. However, wearable EEG systems pose significant challenges for the analog front-end (AFE) circuits in view of μV-level EEG signals of interest, multiple sources of interference, and ill-defined skin contact. This paper presents a direct-digitization AFE tailored for dry-electrode scalp EEG recording, characterized by wide input dynamic range (DR) and high input impedance. The AFE utilizes a second-order 5-bit delta-delta sigma (Δ-ΔΣ) ADC to shape DC electrode offset (DEO) and low-frequency disturbances while retaining high accuracy. A non-inverting pseudo-differential instrumentation amplifier (IA) embedded in the ADC ensures high input impedance (Zin) and common-mode rejection ratio (CMRR). Fabricated in a standard 0.18-μm CMOS process, the AFE delivers 700-mVpp input signal range, 95.3-dB DR, 87-dB SNDR, and 800-MΩ input impedance at 50 Hz while consuming 88.4μW from a 1.2 V supply. The benefits of high DR and high input impedance have been validated by dry-electrode EEG measurement.

The recording of biopotential signals using techniques such as electroencephalography (EEG) and electrocardiography (ECG) poses important challenges to the design of the front-end readout circuits in terms of noise, electrode DC offset cancellation and motion artifact tolerance. In this paper, we present a 2 nd -order hybrid-CTDT Δ∑-∑ modulator front-end architecture that tackles these challenges by taking advantage of the over-sampling and noise-shaping characteristics of a traditional Δ∑ modulator, while employing an extra ∑-stage in the feedback loop to remove electrode DC offsets and accommodate motion artifacts. To meet the stringent noise requirements of this application, a capacitively-coupled chopper-stabilized amplifier located in the forward path of the modulator loop serves simultaneously as an input stage and an active adder. A prototype of this direct-to-digital front-end chip is fabricated in a standard 0.18-μm CMOS process and achieves a peak SNR of 105.6 dB and a dynamic range of 108.3 dB, for a maximum input range of 720 mV pp . The measured input-referred noise is 0.98 μV rms over a bandwidth of 0.5-100 Hz, and the measured CMRR is >100 dB. ECG and EEG measurements in human subjects demonstrate the capability of this architecture to acquire biopotential signals in the presence of large motion artifacts.