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Superconductor–semiconductor hybrid circuits can combine the benefits of the high-speed and low-power operation of single-flux quantum circuits and high integration densities of CMOS technology such as memory. The Suzuki stack, a type of Josephson latching driver/amplifier, is a widely used interface circuit in Josephson–CMOS hybrid memories. Due to the limited cooling power at cryogenic temperatures, the power dissipation is becoming an important concern, especially in large-scale systems. An optimization technique to significantly reduce the power dissipation of Suzuki stack circuits is proposed in this article. The proposed design can reduce the power dissipation by 30–70% while causing a voltage drop of 2–9% in the output voltage depending on the circuit parameter configuration. The tradeoffs between the power dissipation and output voltage characteristics are discussed. The proposed design can operate correctly within at least $\pm$ 20% of process parameter variations as demonstrated with extensive simulations. [ABSTRACT FROM AUTHOR]

Superconducting Josephson junctions and quantum phase slip (QPS) junctions create various hybrid circuits combined with nonsuperconducting elements. Those circuits require a common analysis method to bridge the gap between superconducting and nonsuperconducting electronics. This article presents an electromagnetic-flux-distribution model to unify the analyses of superconducting and non-superconducting circuits. This model uses electric and magnetic fluxes as the variables to unify the definitions of circuit elements and circuit laws; it derives general circuit equations of the circuits viewed from both electric and magnetic fields, to depict their dynamics and duality principles. This method is demonstrated in the analyses of a Josephson junction circuit and its dual QPS junction circuit. It shows that Josephson junction circuits are the magnetic-flux distribution network tuned by the Josephson current, while QPS junction circuits are the electric-flux distribution network modulated by the QPS voltage. [ABSTRACT FROM AUTHOR]

Practical superconducting quantum interference devices (SQUIDs) have been developed into multiloop hybrid electric circuits with Josephson junctions and normal elements such as resistor, inductor and capacitor. To find a common circuit analysis and simulation method for different types of SQUID hybrid circuits consist of both superconducting and normal components, we introduce a mesh-current method, which can derive both the general system model and uniform circuit equations directly from the equivalent circuit. The mesh-current method is demonstrated in the simulation of a SQUID additional positive feedback circuit. The numerical simulation results are presented and verified with the measurements. Compared with the conventional nodal analysis method, the mesh-current method is excellent in dealing with the relations including external flux, self and mutual inductances in multiloop hybrid circuit analysis; its final circuit equations directly exhibit the physical theorems; its general system model reveals the quantum interference mechanism inside SQUID circuits, and is applicable for further dynamics studies. [ABSTRACT FROM AUTHOR]

Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient high-performance information processing systems. Its static power is zero because of ac flux bias, and its dynamic power is considerably reduced, thanks to the adiabatic switching of the junctions. The lack of high-density memories in the AQFP logic, however, makes it challenging to realize large-scale information processing systems with the use of pure AQFP circuits. We have been developing a Josephson-CMOS hybrid memory to overcome the memory bottleneck in AQFP digital systems. By utilizing the high sensitivity of the AQFP gate, the output current from CMOS memories can be significantly decreased resulting in the reduction of the power consumption. In this article, we designed and fabricated a low-power area-efficient AQFP-CMOS hybrid field-programmable gate array (FPGA), where a CMOS memory is utilized as a rewritable read-only memory to control the AQFP circuits. The AQFP circuit for the AQFP-CMOS hybrid FPGA is composed of logic blocks, switch blocks, and connection blocks, which are clocked by four-phase excitation currents. The AQFP-CMOS hybrid FPGA is fabricated by using the AIST 10 kA/cm2 Nb high-speed standard process and the Rohm 0.18 μm CMOS process. The area and power consumption of the two-by-two AQFP logic-cell system are estimated to be approximately 6.56 mm2 and 12.4 nW at 5 GHz operations, respectively. The power consumption of the CMOS memory was estimated to be 1.02 μW assuming the CMOS source voltage of 3 mV. We demonstrated the operation of the AQFP-CMOS hybrid FPGA at low speed by combining the AQFP logic and the CMOS memory. [ABSTRACT FROM AUTHOR]

The dc fault current has a high amplitude and a fast rising speed, therefore with regard to the hybrid dc circuit breaker, it is hard to meet the requirement of a high breaking capacity while maintaining economically efficient. The SI-SFCL can prevent the speed of the fault current from rising too fast, and ensure the current remains under the interrupting capability of the dc circuit breaker, so the couse of the SI-SFCL and the dc circuit breaker is an effective solution for fault clearing in dc grids. In this paper, the current-limiting requirement of the DCCB is given, and a simplified equivalent circuit of the active SI-SFCL is proposed, based on which the matching between the electrical parameters of the active SI-SFCL and the dc circuit breaker is studied. Parameter constraint and the protection voltage range of the active SI-SFCL are given. Finally, the conclusion on the matching between the electrical parameters of the active SI-SFCL and the DCCB is verified by MATLAB/Simulink. [ABSTRACT FROM AUTHOR]

This technical note presents the conceptual design of bidirectional hybrid dc circuit breaker for quench protection circuit (QPC) of the China fusion engineering test reactor. The rated parameter of bidirectional hybrid dc circuit breaker is up to 70 kA and 15 kV. The novel scheme based on a mechanical breaker and the controlled static circuit breaker (SCB) in parallel is proposed. The mechanical breaker consists of three independent control contacts to realize the rapid transfer of the large current and fast recovery of dielectric strength. The SCB is composed of the insulated-gate bipolar transistors (IGBTs) unit and four diode units in a rectifier scheme for both current directions. Moreover, the feasibility of bidirectional dc circuit breaker, such as the turn-on reliability of IGBTs unit, and voltage sharing and current sharing of each IGBTs are investigated in this technical note, finally, the conceptual design result of the QPC is given. [ABSTRACT FROM AUTHOR]

Direct current (DC) circuit breakers are a key enabling technology for fault management in multiterminal highvoltage DC (HVDC) systems. DC fault isolation is challenging due to the high rate of rise of the fault current and the lack of natural current zero-crossings found in ac systems. In this paper, we present a novel superconducting hybrid dc circuit breaker that utilizes the intrinsic characteristics of the superconductor material. The automatic quench of the superconductor coil as a result of a high fault current transfers the current from the mechanical switch to the semiconductor switch. The isolating mechanical switch is able therefore to open at low current and recover its dielectric capability rapidly. A low voltage DC circuit breaker prototype has been built using a multistrand magnesium diboride (MgB2 ) coil, a vacuum interrupter, and an insulated-gate bipolar transistor module. This prototype successfully demonstrated interruption of 500 A DC within 4.4 ms. This paper presents the design of the superconducting hybrid breaker prototype and a detailed analysis of the experimental results. This superconducting hybrid dc circuit breaker has significant potential for scaling up the high-voltage and high-current applications. [ABSTRACT FROM AUTHOR]

This paper presents the results of short-circuit tests with a 22.9 kV hybrid superconducting fault current limiter (SFCL) on the KEPCO test grid. The hybrid SFCL we used for the test had suffered from lots of field tests including a long term operation and it is still in working order. We have already proved that the SFCL showed high reliability as well as feasibility through a long term operation and short-circuit tests performed before. In this paper, we tried to study a dynamic characteristics of the same SFCL on the distribution power grid through short-circuit tests with a circuit breaker and a reclosing relay. An artificial fault generator (AFG) was used to generate fault currents in the KEPCO power test center. The two objectives of the tests are (1) verifying a precise reaction of the SFCL to reclosing operation and (2) a study for protection coordination with SFCL. The test results showed that the SFCL worked precisely with a fast recovery of the superconducting elements when we applied a one-time reclosing operation with the interval of 0.6 second. We also suggested a proper manipulation of the coordination of the protection system in distribution networks with the SFCL in the paper. [ABSTRACT FROM PUBLISHER]

Two identical Nb3Sn coils will be wound at the National High Magnetic Field Laboratory for different series-connected hybrid projects. A model coil with half the length of the production superconducting coil has been fabricated to qualify all fabrication steps. After winding each layer, the impedance spectrum test has been employed to detect short circuits. After impregnation the model coil will undergo a high-voltage surge test which will explore the margin of the layer insulation. Results of impedance testing are reported here. [ABSTRACT FROM PUBLISHER]

High-speed amplification from Josephson-level digital signals of a few millivolts to the volt levels employed in CMOS devices is optimally done in two stages. For the first stage we use a Josephson circuit which amplifies a few-millivolt input to several tens of millivolts. This drives a CMOS digital amplifier. The CMOS amplifier must be calibrated to compensate for random threshold voltage variations in the fabrication process; the design of a digital calibration circuit is included. Simulations of the calibrated amplifier at 300 K show a digital output of 1.8 V with a delay of 70–90 ps when fabricated in a 65 nm CMOS process. Simulations for 4 K will yield better results and are in progress. [ABSTRACT FROM AUTHOR]

We investigated the operational characteristics of the hybrid-type superconducting fault current limiter (SFCL) according to the number of secondary windings. The SFCL consists of a transformer, which has a primary winding and several secondary windings with serially connected YBa2 Cu3O7 films. In order to increase the capacity of the SFCL, the serial connection between each current limiting unit is necessary. Resistive-type SFCL has a difficulty in quenching simultaneously between the units due to slight differences of their critical current densities. The hybrid-type SFCL could achieve the simultaneous quenching through the electrical isolation and the mutual flux linkage among the units. We confirmed that the capacity of the SFCL could be increased effectively through the simultaneous quenching among the units. In addition, the power burden of the system could be reduced by adjusting the number of secondary windings. We will investigate the method to increase the capacity through serial and parallel connections among current limiting units. [ABSTRACT FROM AUTHOR]

Presents a study that seeks to analyze the image hybrid dielectric/high temperature superconductor (HTS) resonator. Use of a full-wave radial mode-matching method; Comparison of measured resonant frequencies and quality factors of single TE01 and dual HE11 modes, with numerical results of the analysis; Estimation of the resonator power-handling capability.