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To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NEC's standard process. We fabricated planarized six-Nb-layer circuit structures using this advanced process. This new structure has four Nb wiring layers for greater design flexibility. To shield the magnetic field produced by the DC bias current, the DC bias power supply layer was placed under the groundplane. The critical current density of the Josephson junction was 10 kA/cm/sup 2/. We fabricated and tested more than 10 wafers and demonstrated that the six-layer circuits were successfully planarized. We also confirmed insulation between each Nb layer and the reliability of superconducting contacts. This planarization did not significantly degrade the junction characteristics. We measured small spreads in the critical current of less than 2%. These results demonstrated the effectiveness of this advanced process based on mechanical-polishing planarization.

The authors evaluated the effect of photomask pattern shape for a counter-electrode on critical current I/sub c/ uniformity and controllability in Nb/AlOx/Nb junctions. Circular, square, and 2 kinds of optical proximity correction (OPC) square patterns were used as the mask pattern shape. Although there was no difference in the I/sub c/ uniformity between square and OPC junctions, the OPC junctions exhibited smaller shrinkage in junction size than the square junction. In addition, the OPC junctions improved the chip-to-chip variation in the shrinkage. The circular junction exhibited the smallest variation in the shrinkage, and had an advantage in I/sub c/ uniformity for smaller than 1.0 /spl mu/m/sup 2/ junctions in comparison with the other junctions. The shrinkage of the circular junction was the largest of all the junctions. This paper describes the recommended choice of the photomask pattern shape for several Nb LSI technologies.

In order to establish double-loop feedback design, we have fabricated a prototype superconducting double-loop lowpass sigma-delta modulator. For digital feedback gain, multiple flux quanta are produced by a ladder circuit and carried through Josephson Transmission Lines (JTLs) to the feedback driver. The feedback driver consists of a single Josephson junction or two serially-connected junctions. Direct injection of the pulse current from the JTLs through a low-value resistor drives the feedback driver. The sigma-delta modulator was operated at the sampling frequency of 1.1 GHz and the measured power spectrum showed the noise shaping roughly of 12 dB/octave, which is characteristic of the second-order sigma-delta modulator.

In order to develop superconducting Digital Signal Processors (DSP's), we have been studying a superconducting 1-bit Arithmetic Logic Unit (ALU). This ALU has the simplest function of AND, OR, ADD (addition), and SUB (subtraction). The ALU operates in a 3-stage pipeline. All logic functions such as AND, OR, and SUM (summation) can be executed within a single stage of the pipeline. In order to achieve the high-speed operation of the ALU, we proposed and designed a novel 3-input XOR gate, which can operate in only one logic stage. Our simulation study showed that all components of the ALU can operate up to 50 GHz. These ALU components were fabricated and tested at low speed. Large bias margins of more than /spl plusmn/37% were achieved. The designed ALU's were laid out and fabricated with an Nb process. The ALU occupied the area of 1200 /spl mu/m /spl times/ 2600 /spl mu/m, which contains 560 Josephson junctions (JJ's).

A third-order sine decimation filter was designed for a /spl Sigma/-/spl Delta/ A/D converter with a second-order modulator. The sine filter was formed from multistage decimation structure, which was constructed from the cascade connection of third-order sine filters with a decimation factor of 2. A counter, consisting of single-flux-quantum (SFQ) toggle flip-flops (TFF) with destructive readout, was used to reduce the circuit scale. The sine filter with a decimation factor of 2, which is the circuit that operates at the highest frequency in a multistage decimation structure, operated up to the clock frequency of 18 GHz in a circuit simulation. A sine filter with a decimation factor of 32 was calculated to require 6700 Josephson junctions that consume 1.9 mW.

We have been developing a superconducting second-order sigma-delta analog-to-digital converter with a large bandwidth and a large dynamic range for software radio applications. In a superconducting second-order sigma-delta modulator utilizing a passive integrator and single-flux-quantum (SFQ) feedback, gain to compensate the large attenuation in the passive integrator of the modulator is required to obtain a large dynamic range. In this paper, a second-order modulator utilizing multi-flux-quantum (MFQ) generators creating the needed gain is reported and the design and experimental test results of the elementary circuits including a comparator, a first-order modulator, and the MFQ generator are described. The digital outputs of the comparator and the first-order modulator were experimentally evaluated, where the input dependence of the comparator switching probability and the noise-shaping properties of the modulator were clearly observed. The low speed operation of the MFQ generator creating three SFQ pulses was experimentally confirmed. The other circuits were also tested at low frequencies.

We have designed ring oscillators to test rapid single flux quantum (RSFQ) circuits with passive transmission lines at high frequencies. To reduce the width of the transmission line, design methods for increasing the characteristic impedance of the transmission line have been investigated and then we designed a 5-stage of Josephson transmission line (JTL) receiver which can transform the impedance from 1 to 4 /spl Omega/ by changing the critical current and the inductance. The receiver, driver, and micro-strip line were inserted in a ring oscillator. The ring oscillator fabricated with the Nb/AlOx/Nb junction process was successfully operated at frequencies ranging from 6 to 10 GHz for line lengths of 0.6, 3, 6, and 9 mm. The usefulness of the impedance transformation was then confirmed experimentally. A propagation delay per unit length of 8.4 ps/mm was also obtained.

We report simulated results of-rapid single flux quantum (SFQ) circuits having driver, receiver, and passive transmission lines for propagating SFQ pulses to investigate the design criteria. We have studied the equivalent input/output resistance of the driver/receiver in various bias conditions and found that the resistance is almost proportional to the bias current of the driver/receiver. Furthermore, we have proposed inserting a series resistor at the end of the superconducting passive transmission line (PTL) for avoiding undesirable flux trapping in the loop and for isolation in regard to the DC current. We also found that the reduction of the bias margin due to the resistance is rather small when the resistance is much smaller than the impedance of the PTL. An operating margin of more than 30% was obtained in the driver/receiver circuits including the PTL and the series resistor.

A mechanical polishing planarization (MPP) process is developed with an endpoint detection method. MPP makes it possible to form self-aligned contacts on small junctions and to decrease parasitic inductance. It can also control the thickness of the insulation layers precisely. MPP was used to fabricate a 22 /spl mu/m/spl times/22 /spl mu/m vortex transitional memory cell and the cell operated correctly. The reliability of interlayer insulation was increased for 64-Kbit memory cell arrays fabricated using MPP. It is concluded that MPP is an effective technology for fabricating high-density Josephson circuits.

A Josephson 256-word/spl times/16-bit RAM that includes a power circuit has been developed to enable high-frequency clock operation. This RAM consists of a 4/spl times/4 matrix array of 256 RAM blocks, impedance-matched lines, and signal amplifiers. A power-supply circuit, composed of a transformer and a Josephson regulator, is included in each 256 RAM block. Fail bit maps for the 256 RAM block were measured, and perfect operation with a 100% bit yield was obtained. The 256 RAM block functioned up to a clock frequency of 1.07 GHz. We succeeded in feeding a large high-frequency current of more than 2 A into the entire 256-word/spl times/16-bit RAM. The 256-word/spl times/16-bit RAM therefore functioned up to a clock frequency of 620 MHz.

We report on the first complete system-level demonstration of a superconducting digital communication system. In today's digital computer and communication systems, managing data flow is a major challenge as the systems have to deal with a huge amount of information. A superconductor device may solve this problem. There have been several attempts to make superconducting switching core circuits, but there have been no complete system-level demonstrations. We have built such a system to demonstrate the efficiency of superconducting devices used in a communication system. Our system is focused on parallel processor communication, and consists of PCs as the processor elements at the three nodes, three interface boxes, and a superconductive chip immersed in a 4.2-K cryostat. The interconnection chip operation is essentially packet switching that was designed with a pipeline ring architecture. The interface box consists of parallel-serial converters, serial-parallel converters, a FIFO output buffer, and a level conversion circuit. The network system operates successfully at approximately 100 MHz, and the clock frequency is restricted by the speed of the interface ICs, not by that of the superconductive chip. We also confirmed the 2-GHz operation of the switching chip, and estimate that the total throughput of the system ran be increased to more than 10 Gbps.

We developed an 8.5 /spl mu/m/spl times/11.5 /spl mu/m vortex transitional (VT) memory cell. The memory cell is the smallest Josephson memory cell ever reported. The cell was fabricated by electron cyclotron resonance plasma etching and bias-sputtering planarization. This is also the first Josephson circuit fabricated with sub-micron minimum feature size. Proper nondestructive read-out operation was verified even after half-selected conditions. An operating margin of /spl plusmn/14% was obtained for control currents I/sub X/ and I/sub Y/. These results are promising for developing a 1-Mbit/cm/sup 2/ density Josephson RAM.

We have developed a Josephson 4-Kbit RAM with improved component circuits and a device structure having two Nb wiring layers. A resistor coupled driver and sense circuit are improved to have wide operating margins. The fabrication process is simplified using bias sputtering, as a result, its reliability is increased. The RAM is composed of approximately 21000 Nb/AlO/sub x//Nb Josephson junctions, Mo resistors, Nb wirings, and SiO/sub 2/ insulators. Experimental results show a minimum access time of 380 ps and power dissipation of 9.5 mW. Maximum bit yield of 84% is obtained in minimum magnetic field of about 20 /spl mu/G. We confirm that most of fail bits are caused by trapped magnetic flux, and the RAM functions properly for 98% of the memory cells after measuring fail bit map several times. >

We have developed the smallest Josephson nondestructive read-out (NDRO) memory cell, called a vortex transitional (VT) memory cell, for a Josephson high-speed 16-Kbit RAM. Its size is 22/spl times/22 /spl mu/m/sup 2/, which is only 16% of the size of previously developed VT memory cells used in Josephson 4-Kbit RAM. This is achieved by developing a vertically integrated device structure and refining small-junction technology. The cell consists of Nb/AlO/sub x//Nb junctions, three Nb wirings, SiO/sub 2/, insulators and Mo resistors. The VT memory cells operate properly, with a large operating margin of /spl plusmn/20%. >

To confirm a gigahertz frequency power supply in a multichip system, three-stage superconductive filter-type powering device (SFPD) chips and a resistive load chip for a 500 gate Josephson device were designed and fabricated. Low-loss capacitors required for this gigahertz operation were also developed. The authors tested the operation of the three-stage SFPDs in a multichip configuration with resistive load. A superconductive power supply with frequencies as high as 2.0 GHz was demonstrated in a multichip system for the first time. For a 2.0-GHz SFPD, normal operation was confirmed with a resonant frequency of 2.1 GHz, a resonant level of -31 dB, and a current gain of 22.4. The 0.1- Omega input impedance of the device system was successfully transformed to 49.9 Omega . >