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This paper focuses on the packaging process and assembly and interlayer dielectrics (ILD) structural stability including mechanical simulation with polymer-encapsulation and redistribution process for 150-µm pitch Pb-free flip chip packaging of low-k/Cu interconnects. Chemical vapor deposition (CVD) type low-k test vehicles with four Cu layers were fabricated using Cu dual damascene process. Polymer encapsulation and metal redistribution (RDL) technology were applied using wafer integration technology to minimize the stress from the solder bump pad to low-k ILD. This polymer encapsulated dicing line (PEDL) was introduced and the result of investigation discussed. Finite element method (FEM) mechanical simulations are per- formed for RDL approach, normal direct bumping, and PEDL. According to the results with shear loading, RDL approach showed less stress than that of direct bumping at the solder joint. Simulation indicated the die corner stress is reduced significantly on chip with PEDL as compared to that without PEDL. For copper postinterconnects, cost-effective and thick photoresist process was developed and optimized for electro Cu plating and solder was deposited on the top of Cu post. Bump shear test was carried out to evaluate the bump quality and failures were analyzed. After flip chip assembly with Cu/low-k devices having via-chain and daisychain interconnects, various JEDEC standard reliability tests were carried out and failure analysis was performed. [ABSTRACT FROM AUTHOR]