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Rapid changes in the semiconductor industry will continue toward higher functionality that leads to higher input/outputs (I/O) counts, pushing packaging towards higher density architectures. In the next two to three years, the I/O pitch will fall within 100 μm for area array die and 30 μm for periphery die. That raises an important question to the packaging industry: How will the rapid shrinkage of the I/O pitch affect the package substrate for chip attaching? The answer is sub-10 micron copper line technology. Theoretical and experimental studies on the limitations of using mercury i-line ultraviolet photolithography have been carried at the Packaging Research Center at Georgia Tech. Furthermore, ultra fine copper line routing substrates are demonstrated for flip chip attaching by using semi-additive metallization process.

The authors demonstrate the fabrication of 1 mm t 1 mm GaN-based power flip-chip light-emitting diodes (LEDs) with an internal electrostatic discharge (ESD) protection diode on Cu sub-mount. With the internal diode, it was found that forward voltage of the LED increased from 3.22 to 3.38 V while output power decreased from 366.5 to 273.9 mW when under 350 mA current injection due to the reduced light emitting area. It was also found that we can achieve a significantly better ESD robustness by building the internal diode inside the LED chip. Furthermore, It was found that 90% of the LEDs with internal diode survived with an applied reverse ESD surge of 12000 V and 25% of the LEDs can even endure 20000 V reverse ESD stressing.

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages, and ball grid arrays, chips/packages are attached to the substrates/printed wiring board (PWB) using solder bump interconnections. Solder bumps hidden between the chips/packages and the substrate/board are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometer techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chip packages, chip scale packages and land grid arrays. The system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response in nanometer scale on the package surface is measured using the interferometer technique. In this paper, wavelet analysis of laser ultrasound signals is presented and compared to previous signal processing methods, such as error ratio and correlation coefficient. The results show that wavelet analysis increases measurement sensitivity for inspecting solder bumps in electronic packages. Laser ultrasound inspection results are also compared to X-ray results. In particular, this paper discusses defect detection for a 6.35 mm × 6.35 mm × 0.6 mm PB18 flip chip package and flip chip package (?SiMAF?) with 24 lead-free solder bumps. These two types of flip chip specimens are both nonunderfilled.

This paper presents the parametric study of RF-via (0-level) and flip-chip bump (1-level) transitions for applications of packaging coplanar RF-MEMS devices. The key parameters were found to be the bumps' and vias' positions and the overlap of the metal pads, which should be carefully considered in the entire two levels of packages. The length of the backside transmission line, determining the MEMS substrate area, showed minor influence on the interconnect performance. With the experimental results, the design rules have been developed and established. The optimized interconnect structure for the two levels of packages demonstrates the return loss beyond 15 dB and the insertion loss within 0.6 dB from dc to 60 GHz.

Current techniques for nondestructive quality evaluation of solder bumps in electronic packages are either incapable of detecting solder bump cracks, or unsuitable for in-line inspection due to high cost and low throughput. As an alternative, a solder bump inspection system is being developed at Georgia Institute of Technology using laser ultrasound and interferometric techniques. This system uses a pulsed Nd:YAG laser to induce ultrasound in electronic packages in the thermoelastic regime; it then measures the transient out-of-plane displacement responses on the package surfaces using laser interferometric technique. The quality of solder bumps in electronic packages is evaluated by analyzing the transient responses. This paper presents a systematic study on thermomechanical reliability of flip chip solder bumps using laser ultrasound-interferometric inspection technique and finite element (FE) method. The correlation between the failure parameter extracted from FE simulation for evaluating solder bump reliability and quality degradation characterization of solder bumps through noncontact, nondestructive laser ultrasound testing has also been investigated. Accelerated thermal cycling (ATC) tests were performed in two phases on flip chip package (FCP) test vehicles with 63Sn37Pb solder bumps. In phase I, four boards were thermal cycled up to 70 cycles. Every ten cycles, the boards were taken out of the chamber and FCPs on each board were tested for detecting presence of cracks using resistance and laser ultrasound testing methods. These measurements were repeated every 10 cycles and stopped after 70 cycles. Laser ultrasound testing results show that starting from 10 cycles, testing values began to increase gradually until 50 cycles when there was a sharp jump (through crack verified at 50 cycles with cross section). Cross section was done only after 70 cycles, and the results show that solder bumps at the corners had through cracks, while solder bumps at the center had partial cracks. Phase II study was a refinement of phase I study. In phase II study, seven boards were thermal cycled starting from 27 cycles to 56 cycles at an increment of approximate five cycles. After every five cycles, only one board was pulled out and tested in order to track crack initialization and propagation in solder bumps. Smaller thermal cycle increments were used in phase II to help determine when cracks initiated and propagated. It was shown that laser ultrasound technique could nondestructively track solder bump crack propagation due to thermal fatigue. The Anand's viscoplastic constitutive model was used in FE simulation to describe the inelastic deformation behavior of solder bumps in thermal cycling. A 3-D FE model was implemented using ANSYS on the same FCP as used in the ATC testing. The stress-strain results were extracted from FE modeling and the inelastic strain energy density (SED) increment per cycle calculated from the critical solder bump was used as a failure parameter. In this paper, it was demonstrated that there is a good correlation between the inelastic SED increment extracted from FE simulation and experimental results from nondestructive laser ultrasound testing.

A locally matched flip-chip (LMFC) interconnect that uses a capacitive compensation technique to minimize impedance mismatch in coplanar waveguide lines is described. With an optimum percentage change in capacitance of 55plusmn5%, we observe return loss below 25 dB over 90% of a 50 GHz bandwidth. When compared to a conventional flip-chip method, the minimum performance improvement in return loss is 10 dB and the insertion loss is smooth up to 30 GHz. The LMFC interconnect consists of two micromachined features: 1) an air cavity underneath the chip and 2) local trenches in the transition region of the flip-chip interconnect interface. A comparison of different LMFC interconnect designs to the conventional flip-chip approach is made, and design rules to obtain local trench dimensions are discussed.

In this paper, we present the design, fabrication process, and experimental results of an electroplated metal buried interconnect and through-wafer via technology suitable for extremely low resistance interconnection of microelectronic devices. The technology is demonstrated using a 3-D daisy-chain test structure comprised of electroplated through-wafer vias buried in the silicon substrate to form the respective interconnect. In contrast to the conventional daisy-chain structures used in flip chip joining and packaging, the designed structure is fabricated on a single substrate without requiring a subsequent bonding process. The top connectors formed on the front-side of the substrate are connected to bottom connectors buried inside the substrate (buried interconnects) through 61-mum-high, void-free, fully-filled, electroplated vias. The metal electroplated buried interconnects are fabricated at the bottom surface of 232-mum-deep trenches formed on the backside of the substrate. Processes for forming deep trenches with rounded-off edges and photoresist spray coating have been developed to fabricate the buried interconnects and complete the daisy-chain structure. Developed processes enable conformal photoresist deposition inside the deep vertical trenches with excellent step and sidewall coverage, surpassing the limitations of conventional fabrication approaches. Furthermore, electroplating molds were perfectly patterned at the bottom of these deep trenches. Through-wafer vias with controllable height are fabricated by direct bottom-up plating from the buried interconnect without additional preparation, such as wafer bonding or hole filling processes. The interconnection scheme developed in this research considerably reduces the height of narrow vertical vias, compared to conventional through-wafer vias, and enables a high density array of interconnect structures. Moreover, low resistance interconnect suitable for high power applications can be realized with thick electroplated copper and fully-filled vias. Buried interconnect can be also utilized in high voltage transistor applications. Resistance testing has been performed to validate the electrical integrity of the fabricated daisy-chain structure, and the results are compared with simulation and analytical calculations.

Competing mechanisms of electromigration and thermomigration in flip chip SnAgCu (SAC) solder joints were studied experimentally. A daisy chain of solder joints were stressed at 2.0 times 104 Amps/cm2, 2.4 times 104 Amps/cm2, and 2.8 times 104 Amps/cm2 current density levels at room temperature. In the test vehicle, some solder joints were exposed to a combination of electromigration and thermomigration, while some others were exposed to thermomigration alone. The changes in the intermetallic compound (IMC) microstructure were observed with scanning electron microscope (SEM) under thermomigration alone and when both migration processes are present. In all cases, Cu6Sn5 IMC at the hot side disintegrated while at the cold side thickened. The dissolution of the IMC at the hot side and the thickening at the cold side is a result of temperature and diffusion driving forces. It is observed that thermomigration driving force, when present, is much larger than electromigration.

Extensive understanding and management of the thermal-mechanical characteristics of novel packaging designs during the bonding process are indispensable to the realization of the technologies. Thus, this paper attempts to explore the bonding process-induced thermal-mechanical behaviors of an advanced flip chip (FC) electronic packaging. FC packaging employs a novel anisotropic conductive film, which is a thin composite film composed of polymer matrix and thousands of millions of highly oriented, 1-D silver (Ag) nanowires on the scale of 200 nanometers in diameter. For carrying out the process simulation, a process-dependent finite element (FE) simulation methodology that integrates both thermal and nonlinear contact FE analyses and a special meshing scheme is applied. The material properties of the nanoscale Ag wires are first explored using molecular dynamics (MD) simulations. By the characterized material properties of the Ag nanowires, the effective material properties of the composite film are derived through two theoretical approaches: 1) the rule-of-mixture (ROM) technique and 2) the proposed FE method-based approach. The predicted results by these two approaches are extensively compared with each other to examine the feasibility of using the widely used ROM technique for such cases. In addition, the validity of the proposed process-dependent FE simulation methodology is also confirmed through three experiments: 1) micro-thermocouple measurement of temperature; 2) Twyman-Green Moire interferometry measurement of out-of-plane deformations; and 3) portable engineering Moire interferometry measurement of in-plane deformations. Throughout the investigation, the effectiveness of the novel interconnect technology is demonstrated. Good agreement with the experiments is also obtained. It is found that the technology may ensure good electrical performance and structural integrity, not only at room temperature but even at elevated temperature, based on its substantial contact stresses but minor peeling stresses on the bonding line, together with a moderate, process-induced warpage on the substrate.

A new type of probe card is designed and fabricated for wafer-level integrated circuit (IC) testing. Using micromachining technology, roughly 18000 cantilever-tip probes can be integrated in one 4-in wafer, with a minimum pitch of 90 mum for adjacent probing tips. The probe card employs a silicon-and-metal composite structure, in which the bulk-micromachined silicon cantilever arrays provide uniform probing height and good planarity for the tips, as well as, the electroplated nickel probing tips feature high hardness and satisfactory electric contact with the pads to be tested. Electroplated nickel is used to simultaneously create the probing tips and the through-wafer interconnects (TWIs), which can transfer the testing signals from the dies-under-test (at the wafer bottom side) to the input/output (I/O) interface (on the front side). The probe card makes full use of the excellent mechanical properties of single-crystal silicon and satisfactory electrical properties of electroplated nickel, with the TWIs facilitating the following solder-bump flip-chip packaging. The fabricated cantilever-tip is able to withstand a contact force of 50 mN, corresponding to a tip displacement of 33 mum. The measured contact resistances on metal thin-film specimens (Al, Cu, and Au) are all below 1 Omega, whereas the maximum current leakage across two adjacent tips is 90 pA at 5 V voltage.

Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm times 6.5 mm with 48 spring contacts on a 0.8 mm times 0.65 mm grid array, each spring measuring 400 mum times 100 mum. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone >20 000 hot plate thermal cycles and >1000 oven thermal cycles without failure.

We report the development of a low cost, simple optical/electrical circuit board (OECB) using multimode polymer waveguide on FR4 printed circuit board (PCB). The design of this OECB uses only a 45deg-ended waveguide to couple and decouple the optical signal directly between the optical devices and the waveguide. The 45deg mirror is formed using excimer laser process on a multimode waveguide with temperature stability at reflow temperature. The optical waveguide is attached to a diced channel in the FR4 PCB using adhesive to form a completely planar circuit. This allows the laser diode and the photodiode to be assembled directly above the input and output of the waveguide using precision flip chip technology, which provides good alignment accuracy. This helps to increase the mechanical reliability of the circuit and minimize assembly requirements. Most importantly, all the electronic and optoelectronic devices used are commercially available components. In the paper, we report the details of the design, simulation result, and the testing results.

Flip chip packaging faces two primary bonding-process obstacles: flux use and geometry mismatch between die and substrate pad pitch. These obstacles motivated the development of a fluxless bonding method called solid-liquid interdiffusion bonding by compressive force (SLICF). SLICF utilizes a mechanical force to form the bond through solid-liquid interdiffusion with a joint-in-via (JIV) architecture for flip chip packaging. SLICF bonding (also known as thermo-mechanical (TM) bonding) forms an instantaneous bond and eliminates the need for reflow infrastructure. Both Au-PbSn and Au-SAC interconnect systems were studied for the SLICF bonding on the JIV architecture at a 130- mum pitch. The morphologies of Au-PbSn and Au-SAC in solid-liquid interdiffusion were studied with their kinetics measured by the Au consumption rate. The SLIFC bonds for Au-PbSn and Au-SAC were compared and assessed by mechanical shear tests and thermomechanical stresses. Au with PbSn was found to perform marginally better due to its joint geometry and slower kinetics.

In this paper, a system-on-package (SOP) technology using a thin-film substrate with a flip-chip interconnection has been developed for compact and high-performance millimeter-wave (mm-wave) modules. The thin-film substrate consists of Si-bumps, ground-bumps, and multilayer benzocyclobutene (BCB) films on a lossy silicon substrate. The lossy silicon substrate is not only a base plate of the thin-film substrate, but also suppresses the parasitic substrate mode excited in the thin-film substrate. Suppression of the substrate mode was verified with measurement results. The multilayer BCB films and the ground-bumps provide the thin-film substrate with high-performance integrated passives for the SOP capability. A broadband port terminator and a V-band broad-side coupler based on thin-film microstrip (TFMS) circuits were fabricated and characterized as mm-wave integrated passives. The Si-bumps dissipate the heat generated during the operation of flipped chips as well as provide mechanical support. The power dissipation capability of the Si-bumps was confirmed with an analysis of DC-IV characteristics of GaAs pseudomorphic high electron-mobility transistors (PHEMTs) and radio-frequency performances of a V-band power amplifier (PA). In addition, the flip-chip transition between a TFMS line on the thin-film substrate and a coplanar waveguide (CPW) line on a flipped chip was optimized with a compensation network, which consists of a high-impedance and low-impedance TFMS line and a removed ground technique. As an implementation example of the mm-wave SOP technology, a V-band power combining module (PCM) was developed on the thin-film substrate with the flip-chip interconnection. The V-band PCM incorporating two PAs with broadside couplers showed a combining efficiency higher than 78%.

This paper presents a comprehensive methodology to model the static temperature-humidity (TH) aging test ( 85 degC/85%RH over 1000 h) of flip chip on flex interconnections with nonconductive adhesives (NCAs). NCAs, being a special form of conductive adhesives, are chosen, as they allow bringing the pitch further down. The methodology combines experimental techniques for material characterization, finite element modeling (FEM), and model validation. A NCA has been characterized using several techniques. The thermomechanical properties and the moisture absorption properties were obtained for the NCA. A temperature dependent viscoelastic constitutive model was also obtained for the NCA. The viscoelastic model was defined by the Prony series expansion. The shift factor was approximated by the Williams-Landel-Ferry (WLF) equation. Finite element modeling has been performed to analyze the flip chip interconnects on flex with the NCA under process condition and reliability aging conditions. The viscoelastic constitutive relation has been used to model the NCA in aging modeling. An integrated process-aging modeling methodology has been developed to combine the thermo-mechanical stress and hygro-mechanical stress, followed by stress relaxation analysis. To verify the finite element models, static TH aging tests (85 deg C/85%RH) were also performed. The contact resistance was monitored with high measuring resolution during the accelerated test. The simulation results are in good agreement with the experimental results. The approach developed in this paper can be used to provide guidelines with respect to adhesive material properties, assembly process parameters to achieve good reliability performance.

The flip chip, a type of chip mounting used in semiconductor devices, has become one of the most popular innovations in the semiconductor packaging industry. The height of flip-chip solder bumps ranges from 20 to 140 mum with a required measurement accuracy of 2 mu m. Three-dimensional (3-D) measurement of flip-chip solder bumps is crucial to flip-chip manufacturing quality and process control. Currently, 3-D measurement systems for flip-chip solder bumps are mainly based on laser scanning techniques. However, they require a high implementation cost, and suffer from low inspection speed due to the physical line-scanning process. In this paper, a fast and cost-effective 3-D measurement system for flip-chip solder bumps is proposed. The proposed system is based on a phase shift technique, in which the phase is accurately shifted by a software-controlled grating using a digital light processing (DLP) unit that allows full-field measurement of a projected flip chip. The DLP unit can provide a higher fringe-contrast pattern at a faster changing time than a liquid crystal display (LCD) panel. Phase shift-based measurement systems require a calibrated system parameter, which is generally considered a fixed value in currently available methods. In this paper, adaptive parameter values, instead of a fixed value, are used to improve measurement accuracy. The proposed system also adopts a fringe-contrast thresholding to solve the pseudo-surface height problem for high reflective solder bumps and low reflective substrate in a flip chip. Experiments have shown that the 3-D measurement of flip-chip solder bumps is very efficient and effective with the proposed system. Computation time of the proposed 3-D measurement system for a 640 x 480 image that contains almost 500 solder bumps is less than 1 s, and measurement accuracy meets the required specification of 2 mum.

Driving voltage and current signals of piezoceramic transducer were measured directly by using digital storage oscilloscope, and interface microcharacteristics of the specimens of flip-chip bonding were inspected by using a transmission electron microscope. Results show such a trend that power curves of badly bonding were much lower than that of hard bonding, and indicated a monitoring system of ultrasonic bonding reliability. The acceleration of ultrasonic vibration was about several ten thousand times as acceleration of gravity, which activates dislocations inside the metal crystalline lattice which act as the fast diffusion channels. Dislocation diffusion is more prominent than the crystal diffusion when the temperature is low. Differing from thermal melting mechanism of the reflow bonding, the ultrasonic bonding is much faster than the reflow solder bonding.

This paper is for process development of assembly technologies used to fabricate the 3-D silicon carrier system-in-package (SiP). The five assembly technologies are wafer thinning, thin flip chip attach on silicon carrier, ultra low loop wire bonding, glass cap fabrication and sealing, and silicon carrier stacking. The developed SiP has three silicon carriers with four flip chip and one wire bond die chip attached to them and the carrier is stacked one above the other to form the 3-D silicon carrier SiP. Eight-inch bumped wafer thinning down to less than 100 mum, lower flip chip interconnect height between the chip and the carrier down to 35 mum, 40-50- mum low loop wire bonding on overhang by direct reverse wire bonding method using 1- mil-di- ameter Au wire are achieved. And investigation of three types of thin film metallization systems for wirebonding and investigation of two different methods in fabricating glass cap are also studied.

This paper presents a feasibility study of using eddy current induced heating for the solder reflow of area array packages. With a high frequency electromagnetic field, Sn 3.5% Ag lead-free solder balls were heated to melt and wet the solder pads on an organic substrate. The experimental results showed that such a solder reflow process could be implemented effectively in a wide processing window. With an infrared temperature sensor, it was found that the temperature difference between the solder balls and the FR4 board might reach 80 , indicating a rather localized heating mechanism. In addition, the heating and cooling rates during the soldering were found very high. This is another feature of the induction heating reflow process. It was also found that the generated temperature in the solder balls would depend on the size of the solder balls. This characteristic may be used to perform selective soldering of flip chip BGA packages. Furthermore, the developed soldering process was applied to the board level reflow of actual components. The result verified that the induction heating reflow is a feasible soldering process in actual applications.

Solder joint reliability of 3-D silicon carrier module were investigated with temperature cycle and drop impact test. Mechanical simulation was carried out to investigate the solder joint stress using finite element method (FEM), whose 3-D model was generated and solder fatigue model was used. According to the simulation results, the stress involved between flip chip and Si substrate was negligible but stress is more concentrated between Si carriers to printed circuit board (PCB) solder joint area. Test vehicles were fabricated using silicon fabrication processes such as DRIE, Cu via plating, SiO deposition, metal deposition, lithography, and dry or wet etching. After flip chip die and silicon substrate fabrication, they were assembled by flip chip bonding equipment and 3-D silicon stacked modules with three silicon substrate and flip chip dies were fabricated. Daisy chains were formed between flip chip dies and silicon substrate and resistance measurement was carried out with temperature cycle test (C, 2 cycles/h). The tested flip chip test vehicles passed T/C 5000 cycles and showed robust solder joint reliability without any underfill material. Drop test was also carried out by JEDEC standard method. More details on test vehicle fabrication and reliability test results would be presented in the paper.

High-speed chip-to-chip interconnect utilizing flex-circuit technology is investigated for extending the lifetime of copper-based system-level channels. Proper construction of the flex ribbon is shown to improve the raw bandwidth over standard FR-4 boards by about three times. Active testing results from a 130-nm CMOS test vehicle show the potential of up to two times higher data rates. The next-generation test vehicle with 90-nm CMOS circuits gives improved voltage and timing margins at 20 Gb/s. In an interconnect limited case a channel with 36 in (91.4 cm) of flex runs at 18.2 Gb/s data rate at a bit-error ratio (BER) of better than 10-12. The channel includes two 90-nm CMOS test chips, two organic flip-chip package substrates, and two flex connectors; crosstalk is not included in this experiment. High-speed connector solutions, including results from a ldquosplit socketrdquo assembly test vehicle, are discussed in detail. The characterization of two top-side flex connector prototypes demonstrates their basic durability and good high-frequency performance. Samples survive 100 mating cycles at an average contact resistance of less than 30 mOmega, adequate for high-speed signaling. Measured differential insertion loss is less than 1.5 dB up to 10 GHz and less than 3.5 dB up to 20 GHz. Near-end and far-end crosstalk measurements indicate that the connectors exceed crosstalk specifications.

Electroplated pure tin bumping as a lead-free alternative for ultra fine pitch applications is a relatively easy process and has provided us with comparable results to eutectic Sn/Pb for thermal cycling reliability. Experimentally, it has been reported that a significantly higher (~40%) thermal cycle fatigue life is seen with the use of cobalt under bump metallization (UBM) instead of copper UBM for a flip-chip device assembled on an alumina substrate. In the current approaches used to estimate fatigue life of solder joints, the solder joint is treated as a homogenous material and modeled as such. However, the smaller joint sizes and higher reactivity of Sn implies that a larger amount of intermetallics are formed as a percentage of bump volume. The existing approach cannot account for the influence on the fatigue behavior of these intermetallic layers within the solder joint. In order to investigate if a simplified engineering approach can provide some insight into this issue, we have attempted to explicitly model the intermetallics as a continuous but separate part of the solder joint. The main damage parameter investigated is the accumulated inelastic strain in a single thermal cycle. From the results, it is clear that the Young's modulus of the intermetallic layer plays an important role, more so when the ratio of intermetallic thickness to the solder joint standoff increases. Thickness of the intermetallic layer also influences the overall strain accumulation in the same manner. The CTE of the intermetallic layer has a relatively lesser influence on the strain accumulation. Both the experimental and FE results suggest that changing the UBM from copper to cobalt can improve the fatigue life by 20%-30%.

Although flip chips have received wide acceptance as an integrated circuit package, significant manufacturing problems exist with the integrity of the connection between the package and the printed circuit board (PCB). Conventional X-ray, ultrasonic and electronic testing systems have been used to assess the integrity of this connection, however, none of these have proven suitable for detecting open solder bumps between the chip and the board. The inability to detect open solder bumps with traditional methods merits the investigation of new, nondestructive methods for detecting defects in a manufacturing environment. This work assesses the feasibility of monitoring the vibration characteristics of flip chips to detect open solder joints. Test vehicles with open solder joints were created, and a nondestructive laser ultrasonic system was used to measure the free vibration response of the chips attached to the printed circuit board. The algorithm of mode isolation (AMI) was applied to the vibration response data in order to extract the modal parameters of the chip. The statistical differences between the modal parameters of sets of damaged and undamaged chips were assessed, revealing the ability of the method to determine the location and severity of these defects in the presence of experimental scatter and manufacturing variation. The parameters of the first mode of vibration, especially its mode shape, were found to be much more sensitive to damage than those of a higher frequency mode.

Performance, power, size, and cost requirements in the microelectronics industry are pushing for smaller feature size, innovative on-chip dielectric materials, higher number of interconnects at a reduced pitch, etc., without compromising the microelectronics reliability. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill material. These compliant interconnects are beneficial for integrated circuits (ICs) with low-K dielectric material. They are also potentially cost effective as they can be fabricated using conventional wafer fabrication infrastructure. In this paper we discuss the assembly and experimental reliability assessment, through thermal cycling, of G-Helix interconnects assembled on an organic substrate. Results from mechanical characterization experiments are also presented. It is shown that the proposed interconnects are not likely to delaminate or crack the low-K dielectric material. Also, a unique integrative approach is discussed, with interconnects having varying compliance for optimum electrical and mechanical performance.

This paper focuses on the packaging process and assembly and interlayer dielectrics (ILD) structural stability including mechanical simulation with polymer-encapsulation and redistribution process for 150-pitch Pb-free flip chip packaging of low-/Cu interconnects. Chemical vapor deposition (CVD) type low- test vehicles with four Cu layers were fabricated using Cu dual damascene process. Polymer encapsulation and metal redistribution (RDL) technology were applied using wafer integration technology to minimize the stress from the solder bump pad to low- ILD. This polymer encapsulated dicing line (PEDL) was introduced and the result of investigation discussed. Finite element method (FEM) mechanical simulations are performed for RDL approach, normal direct bumping, and PEDL. According to the results with shear loading, RDL approach showed less stress than that of direct bumping at the solder joint. Simulation indicated the die corner stress is reduced significantly on chip with PEDL as compared to that without PEDL. For copper postinterconnects, cost-effective and thick photoresist process was developed and optimized for electro Cu plating and solder was deposited on the top of Cu post. Bump shear test was carried out to evaluate the bump quality and failures were analyzed. After flip chip assembly with Cu/low- devices having via-chain and daisychain interconnects, various JEDEC standard reliability tests were carried out and failure analysis was performed.

We experimentally characterize the benefits of using surface-normal mechanically flexible optical waveguides, or optical pillars, for chip-to-substrate optical interconnection. In order to benchmark the performance of the optical pillars, the optical coupling efficiency from a light source to an optical aperture with and without an optical pillar is measured. For a light source with 12deg beam divergence, a 50times150 mum optical pillar improves the coupling efficiency by 2-4 dB compared to pillar-free (free-space) optical coupling. A 30times150 m optical pillar improves the coupling efficiency by 3-4.5 dB. This demonstrates the importance of using optical pillars when small photodetectors (PDs) and dense optical input/outputs (I/Os) are needed. The optical excess losses of 50times150 mum optical pillars are measured to be less than 0.2 dB. Due to the high mechanical flexibility of the pillars, we also demonstrate that optical pillars enhance the optical coupling efficiency between the chip and substrate when they are misaligned in the lateral direction. This is especially important since the coefficient of thermal expansion of the chip and substrate are often mismatched, and preserving optical alignment and interconnection between them is critical during thermal excursions. The lateral mechanical compliance of the optical pillars is also measured and can be as great as 30 mum/mN. The optical pillars are also shown to be compliant under a compressive force thus allowing the optical I/Os to be assembled on nonplanar surfaces such as low-cost organic substrates.

The flip chip technique using conductive adhesives have emerged as a good alternative to solder flip chip methods. Different approaches of the interconnection mechanism using conductive adhesives have been developed. In this paper, test chips with gold stud bumps are flip-chipped with conductive adhesives onto a flexible substrate. An experimental study to characterize the bonding process parameters is reported. Initial results from the environmental studies show that thermal shock test causes negligible failure. On the other hand, high humidity test causes considerable failure in flip chip on flex assemblies. Improvements in the reliability of the assembly are achieved by modifying the shape of the gold stud bumps.

An ultra high-density hybrid integration for micro-electromechanical system (MEMS) mirror chips with several thousand inputs/outputs has been developed. The integration scheme involving flip-chip assembly provides electrical signal to individual mirrors, which is compatible with postprocessing steps of selectively removing the silicon handle and releasing the MEMS mirrors. For the first time, to our knowledge, solder deposition and flip-chip bonding of 3-mum bumps on 5-mum centers of a large array has been demonstrated.

The properties of indium-tin-oxide (ITO)/Ni films as transparent ohmic contacts of nitride-based flip chip (FC) light emitting diodes (LEDs) were studied. It was found that 300degC rapid thermal annealed (RTA) ITO(15 nm)/Ni(1 nm) could provide good electrical and optical properties for FC LED applications. It was also found that 20-mA operation voltage and output power of the 465-nm FC LEDs with ITO/Ni/Ag reflective mirror were 3.16 V and 21 mW, respectively. Furthermore, it was found that output intensity of the proposed LED only decayed by 5% after 1200 h under 30-mA current injection at room temperature.

This paper presents the development and evaluation of a large-area carbon-silicon carbide (C-SiC) based composite board material that has the advantages of organic boards in terms of large-area processability and machinability at potentially low-cost while retaining the high stiffness (> 200 GPa) and Si-matched coefficient of thermal expansion (CTE) (~ 2.5 ppm/degC) of ceramics. Test vehicles were fabricated using C-SiC boards for assessing ultra-fine pitch solder joint reliability without underfill as well as the reliability of high-density wiring with microvias on the board. Finite element reliability models were developed to simulate the thermomechanical behavior of test vehicles. From the finite-element simulations as well as accelerated reliability tests, the high stiffness low-CTE C-SiC boards did not show any premature solder joint fatigue failure or dielectric cracking. Furthermore, the C-SiC boards show minimal via-pad misalignment and support the multilayer buildup structure required to achieve very high wiring density. The modeling and experimental results suggest that the low-cost large-area ceramic matrix composite (C-SiC) has superior thermomechanical properties, and is, therefore, a promising candidate substrate material for the emerging microelectronic systems.

Newer, faster, and smaller electronic packaging approaches with high I/O counts and more complex semiconductor devices are emerging steadily and rapidly. Wafer-level chip scaling package (WLCSP) has a high potential for future electronic packaging. However, the solder joint reliability for a large chip size of about 100 mm2 without underfill remains a troubling issue that urgently requires a solution. To this end, a double-layer WLCSP (DL-WLCSP) with stress compliant layers and dummy solder joint is adopted in this research in order to study the design parameters of enhancing the solder joint fatigue life. To ensure the validity of the analysis methodology, a test vehicle of Rambus DRAM is implemented to demonstrate the applicability and reliability of the proposed DL-WLCSP. The results of the thermal cycling in the experimental test show good agreement with the simulated analysis. Furthermore, to investigate the reliability impact of the design parameters, including solder volume, the arrangement of the die-side and substrate-side pad diameter, second compliant layer thickness, die thickness, and the printed circuit board (PCB) thickness, a design of experiment (DOE) with factorial analysis is adopted to obtain the sensitivity information of each parameter by the three-dimensional nonlinear finite-element models (FEMs). The statistics results of the analysis of variance reveal that the thickness of the second stress compliant layer and the volume of the solder joint can effectively reduce the stress concentration phenomenon, which occurs around the outer corner of the solder joint. In addition, the evident interaction between design parameters can also be obtained. The smaller thermal strains can be achieved through a better combination of design parameters of the geometry so as to provide the actual requirement of the physical information prior to manufacturing

Some of the current assembly issues of fine-pitch chip-on-flex (COF) packages for LCD applications are reviewed. Traditional underfill material, anisotropic conductive adhesive (ACA), and nonconductive adhesive (NCA) are considered in conjunction with two applicable bonding methods including thermal and laser bonding. Advantages and disadvantages of each material/process combination are identified. Their applicability is further investigated to identify a process most suitable to the next-generation fine-pitch packages (less than 35 mum). Numerical results and subsequent testing results indicate that the NCA/laser bonding process is advantageous for preventing both lead crack and excessive misalignment compared to the conventional bonding process

A MEMS scanner has been flip-chip bonded by using electroplated AuSn solder bumps. The microelectromechanical systems (MEMS) scanner is mainly composed of two structures having vertical comb fingers. To optimize the bonding condition, the MEMS scanner was flip-chip bonded with various bonding temperatures. Scanning electron microscopy (SEM) with an energy dispersive X-ray (EDX) spectroscopic system was used to observe the microstructures of the joints and analyze the element compositions of them. The die shear strength increased as the bonding temperature increased. During the thermal aging test, the delamination occurred at the interconnection of the MEMS scanner bonded at 340 degC. It is inferred that the Au layer serving as pad metallization has been dissolved in the molten AuSn solder totally, and subsequently the Cr layer was directly exposed to the AuSn solder. Judging by the results of both die shear test and thermal aging test, the optimal bonding temperature was found to be approximately 320 degC. Finally, using this MEMS scanner, we obtained an optical scanning angle of 32deg when driven by the ac control voltage of the resonant frequency in the range of 22.1-24.5 kHz with the 100-V dc bias voltages

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported

A novel flip chip process is reported in which bare dies are thermosonically bonded to arrays of electroplated copper columns formed on a substrate. The new process is intended as a low-cost, lead-free chip-on-board (COB) interconnection method for high-frequency devices. A detailed study has been performed of the electroplating and thermosonic bonding techniques involved. It was found that oxygen plasma treatment of the resist mask could increase the yield of the fine-pitch (

Electronic portable devices are aimed towards higher response speed with a better viewing resolution display. Nonconductive paste (NCP) and nonconductive film (NCF) are the adhesive materials used in fine-pitch display applications. This study compares two commercially available adhesives for fine-pitch chip-on-flex (COF) applications. The electrical performance of the NCP-bonded COF was better compared to the NCF. The rheological properties of these materials in the initial stages and the mechanical properties of the adhesives after bonding are claimed to be the main factors. The semisolid form of the NCF which melts and flows slowly from the interconnection joints finally reduced the effective contact area in the joint as compared to the NCP. A low-pressure bonding caused entrapment of adhesive in the joints, induced stress accumulation in the Z-direction during high thermal loading, and a high coefficient of thermal expansion mismatch in between bumps, adhesive, and electrode traces on the flexible substrate were the key factors for the degradation of electrical conductivity. A high load of 100 N and above was recommended since the effective contact area built into the interconnection was good and reliable after 400 cycles of a thermal shock test of -55degC-125degC. The NCP with a higher elastic modulus which ensures higher stiffness and stability towards elongation gave a better reliability in this environmental test. Cross sectioning and scanning electron microscopy analysis provide evidence of the effective contact area of the joint before and after the thermal cycle environmental test

A fluxless flip-chip bonding process in hydrogen environment using newly developed Sn-rich Sn-Au electroplated multilayer solder bumps is presented. Cr/Au dual layer is employed as the plating seed layer and the underbump metallurgy (UBM). This UBM design, seldom used in the electronic industry, is explained in some details. To realize the fluxless possibility, proper intermetallic growth over the composite structure is needed. In this connection, we like to point out that it is much harder to achieve fluxless bonding using Sn-rich Sn-Au design than the familiar Au-rich 80Au20Sn eutectic design. This is so because Sn-rich Sn-Au alloys have numerous Sn atoms on the surface that can get oxidized easily while the Au-Sn eutectic alloy at thermal equilibrium consists of only Au5Sn and AuSn compounds. Intermetallic nucleation and growth mechanism of sequential electroplating of Au over thick Sn layer is studied with scanning electron microscope (SEM), energy dispersive X-ray spectroscopy (EDX), and X-ray diffraction method (XRD). It is found that Au-Sn intermetallic forms as Au is plated over the Sn layer and acts as a barrier that prevents the oxidation of the inner Sn layer, making fluxless possibility a reality. It is found that the SnAu intermetallic compounds are randomly distributed in the Sn rich joint making the joint strong. The resulting joints contain few voids as examined by an SEM and a scanning acoustic microscope (SAM) and have a remelting temperature of 217degC-222degC. The plated Sn-Au solder bumps on silicon with 50 mum in height are flip-chip bonded to borosilicate glass substrate. This new fluxless flip-chip bonding process is valuable in many applications where the use of flux is prohibited

This paper describes low-temperature flip-chip bonding for both optical interconnect and microwave applications. Vertical-cavity surface-emitting laser (VCSEL) arrays were flip-chip bonded onto a fused silica substrate to investigate the optoelectronic characteristics. To achieve low-temperature flip-chip bonding, indium solder bumps were used, which had a low melting temperature of 156.7degC. The current-voltage (I-V) and light-current (L-I) characteristics of the flip-chip bonded VCSEL arrays were improved by Ag coating on the indium bump. The I-V and L-I curves indicate that optical and electrical performances of Ag-coated indium bumps are superior to those of uncoated indium solder bumps. The microwave characteristics of the solder bumps were investigated by using a flip-chip-bonded coplanar waveguide (CPW) structure and by measuring the scattering parameter with an on-wafer probe station for the frequency range up to 40 GHz. The indium solder bumps, either with or without the Ag coating, provided good microwave characteristics and retained the original characteristic of the CPW signal lines without degradation of the insertion and return losses by the solder bumps

We propose an advanced structure of optical subassembly (OSA) for packaging of the vertical-cavity surface-emitting laser (VCSEL) array, using (111) facet mirror of the V-groove ends formed in a silicon optical bench (SiOB) and angled fiber apertures. The feature of our OSA can provide a low optical crosstalk between neighboring channels, a low feedback reflection, and a large misalignment tolerance along the V-groove. We describe the optimized design of fiber angle, VCSEL position, and fiber position. The fabricated OSA structure consists of 12 channels of angled fiber array, 54.7deg V-grooves, Au-coated mirrors on (111) end facet of the V-grooves, and flip-chip-bonded VCSEL array on a SiOB. In this structure, the beam emitted from the VCSEL is deflected at the 54.7deg mirror of (111) end facet and propagated into the angled fiber. The angled fiber array was polished by 57deg. Fabricated OSAs showed a coupling efficiency of 30%-50% that is 25 times larger than that obtained from an OSA with a vertically flat fiber array. Our OSA showed large misalignment tolerance of about 90 mum along the longitudinal direction in the V-groove. We fabricated a parallel optical transmitter module using the OSA and demonstrated 12 channels times2.5 Gb/s data transmission with a clear eye diagram

In overmolded flip chip (OM-FC) packaging, interface delamination-particularly at the die/underfill interface-is often expected to be a main type of failure mode. In this paper, a systematic stress analysis is performed by means of numerical simulations for the optimal design of package geometries and materials combinations. The behavior of the interfacial stresses at the die/underfill and die/mold-compound (MC) during the molding process is investigated, followed by a parametric study to examine the effects of the package geometries and materials parameters including the underfill fillet size, die thickness, die size, die standoff height, solder mask design pattern, MC used as underfill material, MC properties, etc., on the interfacial stresses. The results demonstrate that a proper selection of these parameters can mitigate the interfacial stresses, and thus is important for the reliability of the low-cost OM-FC packages

An underfill encapsulant was used to fill the gap between the chip and the substrate around the solder joints to improve the long-term reliability of a flip-chip interconnecting system. The underfill encapsulant was filled by the capillary flow. As a part of the series studies of understanding and analysis of the underfill mechanism, this study was devoted to investigate the effects of the contact angle and the bump arrangement on the underfill flow. The Hele-Shaw flow model, that considered the flow resistance in both the thickness direction between the chip and substrate and the plane direction between solder bumps, was assumed. A modified capillary force model including the effects of the contact angle and the bump arrangement was proposed. The capillary force was formulated based on either quadrilateral or hexagonal bump arrangements. A capillary force parameter was used as an index for comparison of different bump design, including bump diameter, gap height, bump pitch, contact angle, and arrangement. A hexagonal arrangement of solder bumps was found to have a higher capillary force and better underfill efficient