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This paper describes techniques and advances for mesh generation and refinement for the analysis of electrical package structures. After a brief review of meshing techniques, a physically based justification is provided for the basic elements of gridding required to accurately represent the following physical issues: edge-effects, projection gridding for signal return currents, conductor proximity, skin-effect, frequency effects, and dielectrics. These individual gridding components are then incorporated into a comprehensive, global algorithm. Many other meshing issues are addressed, including constraints associated with the underlying electromagnetic calculation kernel, removal of superfluous grid lines, assuring symmetric results for symmetric structures, and consistency related to causality and nonphysical effects. A number of 2D and 3D examples are taken from various codes developed by the author and novel techniques are given for effectively gridding 2D structures having even extreme geometric aspect ratios. [ABSTRACT FROM AUTHOR]

To reduce the product development time and achieve first-pass silicon success, fast and accurate estimation of very-large-scale integration (VLSI) interconnect, packaging and 3DI (3D integrated circuits) thermal profiles has become important. Present commercial thermal analysis tools are incapable of handling very complex structures and have integration difficulties with existing design flows. Many analytical thermal models, which could provide fast estimates, are either too specific or oversimplified. This paper highlights a methodology, which exploits electrical resistance solvers for thermal simulation, to allow acquisition of thermal profiles of complex structures with good accuracy and reasonable computation cost. Moreover, a novel accurate closed-form thermal model is developed. The model allows an isotropic or anisotropic equivalent medium to replace the noncritical back-end-of-line (BEOL) regions so that the simulation complexity is dramatically reduced. Using these techniques, this paper introduces the thermal modeling of practical complex VLSI structures to facilitate thermal guideline generation. It also demonstrates the benefits of the proposed anisotropic equivalent medium approximation for real VLSI structures in terms of the accuracy and computational cost. [ABSTRACT FROM AUTHOR]

Presented here are results and recommendations for reducing coupling between adjacent power islands based on full-wave simulations of a HyperBGA SCM (single-chip module). These simulations highlight the use of IBM's internally developed accelerated full-wave solver based on the precorrected fast Fourier transform approach. Speedups of 100× and memory reductions of 12× are shown for real engineering problems, as compared to direct integral equation solutions. [ABSTRACT FROM AUTHOR]

A new technique is described for reducing computational complexity and improving accuracy of combined power distribution and interconnect noise prediction for wide, on-chip data-buses. The methodology uses lossy transmission-line power-blocks with frequency-dependent properties needed for the multigigahertz clock frequencies. The interaction between delta-I noise, common-mode noise, and crosstalk and their effect on timing is illustrated with simulations using representative driver and receiver circuits and on-chip interconnections. [ABSTRACT FROM AUTHOR]

In this paper, we describe a CAD methodology for the full electrical characterization of high-performance, on-chip data buses. The goal of this methodology is to allow the accurate modeling and analysis of wide, on-chip data buses as early as possible in the design cycle. The modeling is based on a manufacturing (rather than design-manual) description of the back-en d-of- the-line (BEOL) cross section of a given technology and on a full, yet contained, description of the power-ground mesh in which the data bus is embedded. One major. aspect of the resulting electrical models is that they allow the designer to evaluate the wide bus from the three viewpoints of signal timing, crosstalk (both inductive and capacitive), and common-mode signal integrity. Another major aspect is that they take into account such important high- frequency phenomena as the dependence of the current return- path resistance on frequencies. The CAD methodology described in this paper has been extensively correlated with on-chip hard- ware measurements. [ABSTRACT FROM AUTHOR]

In this paper, the self-consistent, frequency-dependent dielectric constant ∊!r@(f) and dielectric loss tan δ(f) of several materials are determined over the range 2 to 30 GHz using a short-pulse propagation technique and an iterative extraction based on a rational function expansion. The simple measurement technique is performed in the time domain on representative printed circuit board wiring. Broadband, fully causal transmission-line models based on these results are generated up to 50 GHz for card wiring using low loss materials including BT, Nelco N4000-13, and Nelco N4000-13SI. Simulation and modeling results highlight the need for the accurate frequency-dependent dielectric loss extraction. Signal propagation based on these results shows very good agreement with measured step and pulse time-do- main excitations and provides validation of the measurement and model generation technique. [ABSTRACT FROM AUTHOR]

This paper describes a methodology for global on-chip interconnect modeling and analysis using frequency-dependent multiconductor transmission lines. The methodology allows designers to contain the complexity of series impedance computation by transforming the generic inductance and resistance extraction problem into one of per-unit-length parameter extraction. This methodology has been embodied in a CAD tool that is now in production use by interconnect designers and complementary metal oxide semiconductor (CMOS) process technologists. [ABSTRACT FROM AUTHOR]