25 results on '"Sunil R. Das"'
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2. On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing.
3. Testing Analog and Mixed-Signal Circuits With Built-In Hardware - A New Approach.
4. Space compactor design in VLSI circuits based on graph theoretic concepts.
5. Crosstalk test pattern generation for dynamic programmable logic arrays.
6. A built-in self-testing method for embedded multiport memory arrays.
7. Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization.
8. Fault simulation and response compaction in full scan circuits using HOPE.
9. An adaptive compressed MPEG-2 video watermarking scheme.
10. Getting errors to catch themselves - self-testing of VLSI circuits with built-in hardware.
11. Measuring availability indexes with small samples for component and network reliability using the Sahinoglu-Libby probability model.
12. Robotic tactile recognition of pseudorandom encoded objects.
13. A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays.
14. Instrumentation applications of multibit random-data representation.
15. An efficient BIST method for non-traditional faults of embedded memory arrays.
16. Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets.
17. Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering.
18. An adaptive path selection method for delay testing.
19. Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities.
20. Space compression revisited.
21. Test-set embedding based on width compression for mixed-mode BIST.
22. Space compaction under generalized mergeability.
23. Guest Editorial Second Special Section of the IEEE Transactions on Instrumentation and Measurement in the Area of VLSI Testing - Future of Semiconductor Test.
24. Guest Editorial First Special Section of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT in the Area of VLSI Testing - Future of Semiconductor Test.
25. Guest editorial [Special section on innovations in VLSI automatic test equipment (ATEs)].
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