37 results on '"Xuan, Zeng"'
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2. BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis.
3. GNN-Cap: Chip-Scale Interconnect Capacitance Extraction Using Graph Neural Network.
4. Unleashing the Power of Graph Spectral Sparsification for Power Grid Analysis via Incomplete Cholesky Factorization.
5. Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners.
6. A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling.
7. Automatic Op-Amp Generation From Specification to Layout.
8. Analog Circuit Yield Optimization via Freeze-Thaw Bayesian Optimization Technique.
9. Fast Statistical Analysis of Rare Failure Events With Truncated Normal Distribution in High-Dimensional Variation Space.
10. Faster Region-Based Hotspot Detection.
11. Correlated Rare Failure Analysis via Asymptotic Probability Evaluation.
12. Hotspot Detection via Attention-Based Deep Layout Metric Learning.
13. An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble.
14. Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble.
15. A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method.
16. Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation.
17. Efficient Rare Failure Analysis Over Multiple Corners via Correlated Bayesian Inference.
18. Efficient Parametric Yield Estimation Over Multiple Process Corners via Bayesian Inference Based on Bernoulli Distribution.
19. Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation.
20. Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning.
21. Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis.
22. Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation.
23. Efficient Memory Partitioning for Parallel Data Access in FPGA via Data Reuse.
24. C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations.
25. Improved Tangent Space-Based Distance Metric for Lithographic Hotspot Classification.
26. Harvesting Design Knowledge From the Internet: High-Dimensional Performance Tradeoff Modeling for Large-Scale Analog Circuits.
27. Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors.
28. Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree.
29. Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography.
30. Efficient Transient Analysis of Power Delivery Network With Clock/Power Gating by Sparse Approximation.
31. MOS Table Models for Fast and Accurate Simulation of Analog and Mixed-Signal Circuits Using Efficient Oscillation-Diminishing Interpolations.
32. Binning Optimization for Transparently-Latched Circuits.
33. Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill.
34. Multicore Parallelization of Min-Cost Flow for CAD Applications.
35. Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process.
36. A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm.
37. Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets.
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