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2. Multi-swarm Optimization of a Graphene FET Based Voltage Controlled Oscillator Circuit.
3. Statistical Analysis of Resource Usage of Embedded Systems Modeled in EAST-ADL.
4. Development of a Layout-Level Hardware Obfuscation Tool.
5. High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino Inverter.
6. Message from the General and Program Chairs.
7. Communication-Aware Parallelization Strategies for High Performance Applications.
8. On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.
9. A Full-Swing CMOS Current Steering DAC with an Adaptive Cell and a Quaternary Driver.
10. Toward Adaptation of ADCs to Operating Conditions through On-chip Correction.
11. 3D DFT Challenges and Solutions.
12. The Solar Cells and the Battery Charger System Using the Fast and Precise Analog Maximum Power Point Tracking Circuits.
13. Energy-Aware Computing via Adaptive Precision under Performance Constraints in OFDM Wireless Receivers.
14. On the Performance Exploration of 3D NoCs with Resistive-Open TSVs.
15. Multilevel Modeling Methodology for Reconfigurable Computing Systems Based on Silicon Photonics.
16. On Analysis of On-chip DC-DC Converters for Power Delivery Networks.
17. A Timing Error Mitigation Technique for High Performance Designs.
18. Implementation of AES Using NVM Memories Based on Comparison Function.
19. Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing.
20. Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits.
21. Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design Perspective.
22. Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs.
23. Heterogeneous Error-Resilient Scheme for Spectral Analysis in Ultra-Low Power Wearable Electrocardiogram Devices.
24. A Summary of Current and New Methods in Velocity Selective Recording (VSR) of Electroneurogram (ENG).
25. Digital Right Management for IP Protection.
26. Identification of IP Control Units by State Encoding.
27. Equivalence Checking Using Trace Partitioning.
28. An Improved Dynamic Latch Based Comparator for 8-Bit Asynchronous SAR ADC.
29. A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch Effect.
30. Reducing the Storage Requirements of a Set of Functional Test Sequences by Using a Background Sequence.
31. Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning.
32. Logic Debugging of Arithmetic Circuits.
33. Exploiting Circuit Duality to Speed up SAT.
34. Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power.
35. Index-Based Round-Robin Arbiter for NoC Routers.
36. Efficient Utilization of Imprecise Blocks for Hardware Implementation of a Gaussian Filter.
37. In-silico Phantom Axon: Emulation of an Action Potential Propagating Along Artificial Nerve Fiber.
38. Copyright Page.
39. Cover Art.
40. Publisher's Information.
41. Implementing Data Structure Using DNA: An Alternative in Post CMOS Computing.
42. Built-In Self Optimization for Variation Resilience of Analog Filters.
43. Flexible Ultra-Low-Voltage CMOS Circuit Design Applicable for Digital and Analog Circuits Operating below 300mV.
44. Silicon Demonstration of Statistical Post-Production Tuning.
45. A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy.
46. Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects.
47. Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs.
48. SymmTop: A Symmetric Circuit Topology for Ultra Low Power Wide Temperature-Range Applications.
49. Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE Architectures.
50. Design of Fault-Tolerant and Reliable Networks-on-Chip.
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