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Capability Hardware Enhanced RISC Instructions (CHERI) supplement the conventional memory management unit (MMU) with instruction-set architecture (ISA) extensions that implement a capability system model in the address space. CHERI can also underpin a hardware-software object-capability model for scalable application compartmentalization that can mitigate broader classes of attack. This article describes ISA additions to CHERI that support fast protection-domain switching, not only in terms of low cycle count, but also efficient memory sharing with mutual distrust. The authors propose ISA support for sealed capabilities, hardware-assisted checking during protection-domain switching, a lightweight capability flow-control model, and fast register clearing, while retaining the flexibility of a software-defined protection-domain transition model. They validate this approach through a full-system experimental design, including ISA extensions, a field-programmable gate array prototype (implemented in Bluespec SystemVerilog), and a software stack including an OS (based on FreeBSD), compiler (based on LLVM), software compartmentalization model, and open-source applications. [ABSTRACT FROM AUTHOR]

Silicon interposers enable the integration of multiple stacks of in-package memory to provide higher bandwidth or lower energy for memory accesses. Once the interposer has been paid for, there are new opportunities to exploit the interposer. In this article, the authors exploit the interposer to "disintegrate" a multicore CPU chip into smaller chips that collectively cost less to manufacture than a single large chip. They study the performance-cost tradeoffs of interposer-based, multichip, multicore systems and propose new interposer network-on-chip (NoC) organizations to mitigate the performance challenges while preserving the cost benefits. Although this article focuses on NoC support for disintegrated systems, it paves the way for a range of new research problems in interposer-based disintegrated systems. [ABSTRACT FROM PUBLISHER]

The article proposes Atom-Aid, which is a method for reducing the risk of atomicity violations in the processing of consecutive dynamic memory operations grouped into atomic blocks. The reduction in the opportunities for interleaving between memory operations that results from the application of a computer architecture which provides implicit atomicity is noted, mentioning that Atom-Aid intelligently creates implicit atomic memory blocks in such a way that atomicity violations are much less likely to appear.

The article presents two techniques for operating microprocessors at low voltages. The function of the techniques is described, noting their identification and incapacitation of defective portions of the cache at the granularities of individual words or pairs of bits. The usage of the entire cache by both techniques while operating at high voltages is noted, mentioning that the techniques reduce the capacity of the cache while operating at low voltages to reduce the minimum voltage to levels that are below 500 millivolts (mV).

The article discusses the company AMD's next-generation mobile microprocessor, called Griffin, which focuses on mobile-optimized northbridge design which balances performance and power. Mobile designs require trade-offs among performance, power consumption, and thermal constraints. When using a unified memory architecture for graphics, the northbridge must handle the needs of graphics and central processing unit access to the same shared memory. The innovations Griffin includes to address these challenges, including a memory controller, are discussed.

The article focuses on the functions of Argus, an approach for detecting errors in simple microprocessor cores. It cites that Argus could check the four activities performed by a von Neumann processor core which include control flow, data flow, computation, and memory access. It also discusses the functions of Argus-1, an implementation of Argus that has the same abilities as Argus except for false negatives. Moreover, it looks into how Argus-1 is integrated into the OR1200 processor core as well as its error detection coverage, area and performance overheads, control-flow, and data-flow checkers.

The article presents a study on No Store Queue (NoSQ) microarchitecture to perform in-flight store-load forwarding structures. It explores the speculative memory bypassing (SMB) in converting in-window store-load communication. NoSQ mentions that it repurposes the register read ports and address generation units, which is used to execute stores in the out-of-order core to now execute stores in order. It features other proposed core data path design that contains no dedicated in-flight store-load communication structure. It highlights that NoSQ uses SMB to replace the conventional store-load forwarding path in an out-of-order processor.

The article presents information on a new technique, coarse-grain coherence tracking (CGCT), and its implementations, RegionScour and Region Coherence Arrays. CGCT increases a conventional coherence mechanism and optimizes coherence enforcement. CGCT permits a processor to determine in advance that a request does not require a broadcast. It can be equipped as a layered extension to a conventional multiprocessor system with a modest amount of hardware. This hardware follows the memory regions from which the processor is caching lines and prys external requests to provide a region snoop response. It can enlarge broadcast-based systems to achieve many of the benefits of directory-based systems, including low interconnect and cache tag traffic and low-latency access to non-shared data. A RegionScout filter is composed of two structures located in each processor including a cached-region hash for tracking data cached by the processor and a nonshared-region table for tracking the global state of regions. Whereas, the Region Coherence Arrays are marked structures located in each processor. Each entry holds an address tag, a count of lines cached by the processor, and a protocol state summarizing the local and external states of lines in the region.

The article characterizes the performance evaluation of the Cray XI distributed shared-memory system and its interconnection network using microbenchmarks and applications. The Cray Xl is an attempt to incorporate the best aspects of previous Cray vector systems and massively parallel processing systems into one design. The Cray XI supercomputer's distributed shared memory presents a 64-bit global address space that is directly addressable from every MSP with an interconnect bandwidth per computation rate of 1 byte/flop. The Xl compiler has two options for using the eight vector units of a single MSP. First, it can use all eight when vectorizing a single loop. Second, it can split up the work in an unvectorized outer loop and assign it to the four single-streaming processors, each with two vector units and one scalar unit. Four MSPs, 16 memory controller chips , and 32 memory daughter cards form a Cray Xl node. Results show that this high bandwidth and low latency for remote memory accesses translate into improved application performance on important applications.

The author proposes a novel Reduced Instruction Set Computer (RISC) processor architecture that introduces the robustness gained by garbage collection at the machine-code level. The architecture provides the basis for a hardware garbage collector that closely cooperates with the processor. The advantages of this configuration include low garbage collection overhead, low-cost synchronization of collector and application programs, high robustness, and hard real-time capabilities. The article summarizes the most commonly used garbage collection methods and points out problems of contemporary software-based solutions to motivate architectural support for garbage collection. This article introduces a processor architecture that strictly separates pointers from nonpointer data, allowing for tag-free pointer identification. The processor architecture's memory model is object-based. The processor will operate without a hardware garbage collector as long as the operating system provides a software garbage collector.

Presents information on the application of memory management capabilities to the computer network interface, to allow user-level messaging, while focusing on the U-Net user-level network architecture. Features of the U-Net user-level networking architecture; Implementation of the U-Net/Memory Management (MM) architecture; How the U-Net/MM performed. INSET: Related work.