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A third-order single-loop continuous-time sigma-delta modulator (CTSDM) with 6-bit asynchronous successive approximation register (ASAR) quantizer and digital \Delta \Sigma truncator for WCDMA/GSM/EDGE cellular systems is presented. The proposed ASAR-based quantizer reduces the area and power of the modulator dramatically by utilizing the digital truncation technique. By using the 6-bit ASAR quantizer, the sampling frequency is lowered, which reduces the design efforts not only in system level but also in the modulator. In addition, the ac-coupled push–pull stage is employed to improve the high-frequency driving capability of the first integrator. Sampling at 65 MHz, the modulator achieves 83.4 dB dynamic range (DR) and 80/79.6 dB peak SNR/SNDR with 1.92 MHz bandwidth in WCDMA mode. In GSM/EDGE mode, the DR is 96.2 dB. Fabricated in 40-nm CMOS, the modulator occupies 0.051 mm^2 and consumes 1.91 mW from a 1.2-V supply. A 64fJ/conv.-step figure of merit is achieved. [ABSTRACT FROM AUTHOR]

A VCO is implemented in an RF 90 nm CMOS process and covers the frequency range 2.55–4.08 GHz. Drawing 19 mA from 1.2 V, the phase noise at 20 MHz frequency offset from a 3.7 GHz carrier is -156~\dBc/\Hz, meeting the phase noise requirement for GSM/EDGE and SAW-less WCDMA transmitter after frequency division by 2 or by 4. A second version of the VCO covers an additional 4.90–5.75 GHz range, at the expense of a higher phase noise in the added band. In this way, all currently operational WCDMA/EDGE bands can be synthesized by a single VCO working at the double or quadruple of the desired band. [ABSTRACT FROM AUTHOR]

In cellular applications, open-loop small-signal polar transmitters offer several advantages such as low power consumption and small silicon area. However, due to their complexity, circuit imperfections can severely affect performance, potentially rendering them impractical to meet the challenging cellular transmitter requirements. In this paper a detailed analysis of the direct-modulated and small-signal polar transmitters for GSM/EDGE/WCMA applications are provided followed by some case studies. Several key non-idealities will be discussed and circuit level as well as architectural remedies for each will be presented. A prototype EDGE transmitter fabricated in 65 nm CMOS with an 8PSK \pm400 kHz modulation spectrum of -64/63 dBc for high/low bands, and an RMS EVM of 2.5/2.0% will be discussed. [ABSTRACT FROM AUTHOR]

A quad-band 2.5G SoC integrating all the RF, DSP, ARM, audio and other baseband processing functions into a single 65 nm CMOS die is described. The paper focuses on the radio portion mostly, and addresses the challenges of realizing a complete GSM/EDGE SoC with the RF integrated along with the rest of digital baseband circuitry. Several circuit level as well as architectural techniques are presented to realize a very low-cost and low-power 2.5G radio while meeting the stringent cellular requirements with wide margin. The radio draws a battery current of 49 mA in the receiver-mode, and 86/77 mA in the GMSK/8PSK transmit-mode. The low-IF receiver achieves a sensitivity of -110 dBm at the antenna, corresponding to a noise figure of 2.4 dB at the device input. The 8PSK\pm400 kHz modulation mask is -64.1/62.7 dBc for high/low bands, with an RMS EVM of 2.45/1.95%. The radio core area is 3.95 mm^2. [ABSTRACT FROM AUTHOR]

In this paper we present a multi-band CMOS transmitter for cellular applications. The transmitter covers a wide range of frequency bands and it is designed to minimize power consumption in order to increase handset talk-time. The output noise performance allows the removal of SAW for certain W-CDMA and CDMA bands; moreover it can be configured to be used for SAW-less GSM/EDGE operations while maintaining an excellent linearity. [ABSTRACT FROM AUTHOR]

A digitally modulated power amplifier (DPA) in 1.2 V 0.13 μm SOI CMOS is presented, to be used as a building block in multi-standard, multi-band polar transmitters. It performs direct amplitude modulation of an input RF carrier by digitally controlling an array of 127 unary-weighted and three binary-weighted elementary gain cells. The DPA is based on a novel two-stage topology, which allows seamless operation from 800 MHz through 2 GHz, with a full-power efficiency larger than 40% and a 25.2 dBm maximum envelope power. Adaptive digital predistortion is exploited for DPA linearization. The circuit is thus able to reconstruct 21.7 dBm WCDMA/EDGE signals at 1.9 GHz with 38% efficiency and a higher than 10 dB margin on all spectral specifications. As a result of the digital modulation technique, a higher than 20.1% efficiency is guaranteed for WCDMA signals with a peak-to-average power ratio as high as 10.8 dB. Furthermore, a 15.3 dBm, 5 MHz WiMAX OFDM signal is successfully reconstructed with a 22% efficiency and 1.53% rms EVM. A high 10-bit nominal resolution enables a wide-range TX power control strategy to be implemented, which greatly minimizes the quiescent consumption down to 10 mW. A 16.4% CDMA average efficiency is thus obtained across a > 70 dB power control range, while complying with all the spectral specifications. [ABSTRACT FROM AUTHOR]

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a directconversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1° RMS phase error and the measured phase noise is -164.5 dBcIHz at 20 MHz offset from a 914.8 MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 dB gain step for the overall 36 dB dynamic range. The RX NF and 11P3 are 2.7 dBI12 dBm for the low bands (850/900 MHz) and 3 dB/-11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 μm CMOS technology and occupies 10.5 mm[sup2]. The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in aS x 5mm[sup2] 40-pin QFN package. [ABSTRACT FROM AUTHOR]

This paper describes the design and performance of a 90 nm CMOS SAW-less receiver with D1gRF interface that sup- ports 10 WCDMA bands (I, II, III, IV, V, VI, VIII, IX, X, XI) and 4 GSM bands (GSM850, EGSM900, DCS1800, PCS1900). The receiver is part of a single-chip SAW-less transceiver reference plat- form IC for mass-market smartphones, which has been designed to meet Category 10 HSDPA (High Speed Downlink Packet Access) requirements. The novel receiver core consists of a single- stage transconductance amplifier (TCA) with large gain control range, a current commutating passive mixer enhanced for automatic on chip IIP2 calibration with 25% duty-cycle LO injection and threshold adjust, and current-input complex Direct Coupled Filter (DCF). The low noise TCAs are designed without inductive loads to save area. A self-contained on chip automatic IIP2 calibration system with algorithm routine, implemented in firmware, is used to optimize IIP2 performance. This topology eliminates the external LNA, inter-stage SAW filter and transimpedance amplifier (TZA) in conventional WCDMA designs and results in current drain and die area savings as well as improved noise. The 25% duty-cycle LO injection, with threshold adjustment, into a current driven passive double-balanced mixer results in 3 dB additional gain, lower noise figure and lower intermodulation distortion. Large signal blocking and 1/f noise performance are improved significantly by eliminating the 0 and 180° LO signal crossover at the mixer. The full receiver achieves 2.2 dB/2.39 dB simplex/duplex NF (with -24.5 dBm TX leakage), >90 dBm complex two-tone IIP2, 60 dB gain and - 1/ +5 dBm half/full-duplex image IIP3. The receiver core consumes only 15.1 mA from a 1.5 V supply. [ABSTRACT FROM AUTHOR]

This paper presents a hybrid switching amplitude modulator for class-E2 EDGE polar transmitters. To achieve both high efficiency and high speed, it consists of a wideband buffered linear amplifier as a voltage source and a PWM switching amplifier with a 2 MHz switching frequency as a dependent current source. The linear amplifier with a novel class-Aft topology has a high current-driving capability of approximately 300 mA with a bandwidth wider than 10 MHz. It can also operate on four quadrants with very low output impedance of about 200 mtl at the switching frequency attenuating the output ripple voltage to less than 12 mVpp,A feedforward path, a PWM control, and a third-order ripple filter are used to reduce the current burden of the linear amplifier. The output voltage of the hybrid modulator ranges from 0.4 to 3 V for a 3.5 V supply. It can drive an RF power amplifier with an equivalent impedance of 4 Ω up to a maximum output power of 2.25 W with a maximum efficiency of 88.3%. The chip has been fabricated in a 035 μm CMOS process and occupies an area of 4.7 mm2 [ABSTRACT FROM AUTHOR]

A complete mixed-signal front-end CMOS chip is presented, supporting GSM/EDGE as well as enhanced audio applications. The chosen solution for the transmit section is based on Laurent's approximation of the nonlinear GMSK modulator. This enables burst shaping in the I/Q domain thereby solving the problem of power ramping. Also, up to GPRS class 12 is supported. The receive section on the other hand consists of a low power dual mode continuous-time ΣΔ ADC for I and Q, supporting ZIF and LIF modes of operation and achieving typically 12.5 bit of resolution under production conditions. An on-chip PLL, which supplies all blocks with various clock frequencies, additionally supports clock jitter suppression. The audio section comprises a codec supporting standard formats such as IIS and PCM. It features mono/stereo signaling from various sources in 16 bit quality as well as high-drive buffers for 4 Ω single-ended loads (capacitively coupled). The whole chip is powered from a 1.5/2.65 V supply voltage and consumes 22 mW in paging mode. [ABSTRACT FROM AUTHOR]

The addition of 8PSK modulation to the GSM standard creates the need for architectural modifications to achieve necessary performance while maintaining a cost-effective solution. A large-signal polar modulation transmitter allows the use of an efficient nonlinear power amplifier (PA) for both GMSK and 8PSK. Digital interfaces are used for both receiver and transmitter, with analog options available for compatibility with older technology baseband systems. The receiver section of the transceiver is programmable to operate in direct conversion mode or multiple VLIF modes. All analog and digital filtering necessary to define the final channel is included. The transmit section of the transceiver uses an all digital system with a fractional-N digital modulator for the phase path. The amplitude path uses a Powerstar PA with both the ramp and the amplitude modulation applied to the collector. The transceiver meets or exceeds all specifications for both GMSK and 8PSK in all four cellular bands (850/900/180011900). [ABSTRACT FROM AUTHOR]

This paper describes the design and performance of the first tri-band (2100, 1900, 800/850 MHz) single-chip 3G cellular transceiver IC for worldwide use. The transceiver has been designed to meet all narrowband blocker, newly proposed Adjacent Channel II, and Category 10 HSDPA (High Speed Downlink Packet Access) requirements. The design is part of a reconfigurable reference platform for multi-band, multi-mode (GSM/EDGE + WCDMA) radios. The zero-IF receiver is comprised of a novel multi-band quadrature mixer, seventh-order baseband filtering, and a novel DC offset correction scheme, which exhibits no settling time or peak switching transients after gain steps. The receiver lineup is designed to optimize HSDPA throughput and minimize sensitivity to analog baseband filter bandwidth variations. The direct-launch transmitter is made up of a third-order baseband filter, an I/Q modulator with variable gain, an integrated transformer, an RF variable gain amplifier, and a power amplifier driver. At +9.5-dBm output power, the transmitter achieves an error vector magnitude (EVM) of 4%. Fractional-N synthesizers achieve fast lock times of 50 μs (150 μs) within 20 ppm (0.1 ppm). Automatically calibrated, integrated VCOs achieve a 1.6-GHz tuning range to facilitate coverage over all six 3GPP frequency bands. The IC draws 34 mA in receive (18-mA receiver plus 16-mA fractional-N PLL/VCO) and 50 to 62 mA in transmit (-76 dBm to +9.5 dBm), including PLL/VCO, using a 2.775-V supply voltage. The RF transceiver is integrated with the baseband signal processing and associated passives in a 165-pad package, resulting in the first tri-band 3G radio transceiver with a digital interface which requires no external components. [ABSTRACT FROM AUTHOR]

This work presents a fully integrated linearized CMOS RF amplifier, integrated in a 0.18-µm CMOS process. The amplifier is implemented on a single chip, requiring no external matching or tuning networks. Peak output power is 27 dBm with a power-added efficiency (PAE) of 34%. The amplitude modulator, implemented on the same chip as the RF amplifier, modulates the supply voltage of the RF amplifier. This results in a power efficient amplification of nonconstant envelope RF signals. The RF power amplifier and amplitude modulator are optimized for the amplification of EDGE signals. The EDGE spectral mask and EVM requirements are met over a wide power range. The maximum EDGE output power is 23.8 dBm and meets the class E3 power requirement of 22 dBm. The corresponding output spectrum at 400 and 600 kHz frequency offset is -59 dB and -70 dB. The EVM has an RMS value of 1.60% and a peak value of 5.87%. [ABSTRACT FROM AUTHOR]

This paper describes a highly digitized direct con- version receiver of a single-chip quadruple-band RF transceiver that meets GSM/GPRS and EDGE requirements. The chip uses an advanced 0.25-µm BiCMOS technology. The I and Q on-chip fifth-order single-bit continuous-time sigma-delta (ΣΔ) ADC has 84-dB dynamic range over a total bandwidth of ±135 kHz for an active area of 0.4 mm². Hence, most of the channel filtering is realized in a CMOS. IC where digital processing is achieved at a lower cost. The systematic analysis of dc offset at each stage of the design enables to perform the dc offset cancellation loop in the digital domain as well. The receiver operates at 2.7 V with a current consumption of 75 mA A first-order substrate coupling analysis enables to optimize the floor plan strategy. As a result, the receiver has an area of 1.8 mm². [ABSTRACT FROM AUTHOR]

An enhanced data-rates for GSM evolution (EDGE) transmitter using a nonlinear GSM-type PA is presented. It is based on a novel polar loop architecture that employs separate feedback control of the amplitude and the phase of the output signal. With this approach, the problems with AM-to-PM as well as AM-to-AM of the nonlinear PA are essentially eliminated. In addition, this architecture allows for a large dynamic output power control range, as required by the GSM specification. The transmitter uses a standard I/Q interface and does not require the extraction of amplitude and phase modulation in the digital domain. The dual feedback loop ensures robust performance even under voltage-standing wave ratio variations without using an isolator. No external PA filtering is required to meet the transmitter noise in the receive band. The EDGE spectral mask is met with an rms error vector magnitude of <3 % at 29 dBm at the antenna, corresponding to 2 dB above nominal maximum output power. There is no mode change between GMSK and EDGE, and the transmitter operates seamlessly in multislot Enhanced General Packet Radio Service. The polar modulation transmitter meets or exceeds the GSM-type approval requirements for both EDGE and GMSK in quad band (850/900/1800/1900 MHz). [ABSTRACT FROM AUTHOR]