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This article presents a frequency reference system that combines high frequency accuracy and low power consumption using a single-point temperature trim and batch calibration. The system is intended as a low-cost fully integrated crystal oscillator replacement. In this system, the oscillation frequency of a power-efficient, but process, voltage, temperature (PVT) and lifetime (L)-sensitive current-controlled ring oscillator (CCO) is periodically (re)calibrated by the well-behaved frequency stability of an untuned LC –based Colpitts oscillator (LCO), which is optimized for stability over PVT variations and lifetime (PVTL). During the single-point room temperature factory trim, the frequency of the LCO is determined and the result is digitally stored. An on-chip calibration engine tunes the CCO to the target frequency based on the LCO frequency, temperature sensor information, and digitally stored trimming information, thus effectively improving the frequency stability of the ring oscillator. The relatively high-power LCO is heavily duty-cycled to minimize the overall power consumption. A prototype fabricated in a 0.13- μ m CMOS SOI process and assembled in a plastic package demonstrates an inaccuracy lower than ± 93 ppm over a temperature range from − 63 ∘ C to 165 ∘ C across samples. The presented frequency reference system, including on-chip voltage regulators and a temperature sensor, occupies a chip area of 0.69 mm 2 and consumes about 64 μ A from a single 3.3-V supply. The frequency error due to supply variation is roughly 92 ppm/V. The mean frequency shift due to aging, measured before and after a six-day storage bake at 175 ∘ C, is only 52 ppm.

High common-mode rejection ratio (CMRR) with concurrent electrode offset rejection is essential for physiological signal acquisitions. This article presents a CMRR enhancement technique for ac-coupled instrumentation amplifiers (ACIAs), where the mismatch of passive components limits the CMRR performance primarily. A modified chopping structure is proposed to mitigate the mismatch effect of the pseudoresistors, and a successive-approximation based capacitor trimming loop is exploited. Fabricated in a 0.18- $\mu \text{m}$ CMOS technology, the ACIA draws $2.3~\mu \text{A}$ from a 1.2-V supply and exhibits 3.2- $\mu \text{V}\mathrm {_{rms}}$ input-referred noise over 0.5–400 Hz. The measured prototypes achieve > 110-dB CMRR at 50/60 Hz without any off-chip tuning.

This article proposes an ultralow-power accurate current reference that generates 1-nA current. Since an automatic calibration circuit periodically calibrates the generated current of the current reference, the current reference is able to achieve ultralow power consumption and high accuracy simultaneously without employing a multiple temperature trimming. Prototype chips are fabricated in a 180-nm CMOS technology and are tested with a field programmable gate array (FPGA) board that controls the timing of the calibration. When the calibration is activated every 25 min, measurement results show that the current reference achieves a temperature coefficient of 289 ppm/°C and a line sensitivity of 1.4%/V with no help from a multiple temperature trimming. Estimated total power consumption is 4.5 nW at 23 °C, including the power consumption of a wake-up timer.

In this paper, a novel 4T-2R self-aligned nitride (SAN) cell-integrated static random-access memory (SRAM) cell is first implemented for true random number generator (TRNG) applications. The SRAM can be latched to either state by the unpredictable random telegraph noise (RTN) on the contact RRAMs (CRRAMs). With a self-convergent trimming mechanism, mismatches in SRAM cells due to process variation can be effectively reduced, enabling the small RTN signal to toggle the states randomly. In addition, the numbers generated by the random toggle in the cross-couple latch can be stored directly. Through a series of standard randomness tests, the feasibility, stability of randomness, unpredictability, and long-run continuity of the full logic compatible SRAM TRNG have been demonstrated, making it a promising solution for data security and identification in advanced CMOS-integrated circuits (ICs).

We present a 1-V precision voltage reference with a programmable temperature coefficient (“ temp-co ”). The voltage reference is based on a parasitic bipolar junction transistor (BJT) realized within the process steps available in the chosen 7-nm FinFET technology. Details of its characterization and SPICE modeling are presented to provide insight into key device–circuit optimization choices. The trimming techniques needed to cope with process spread together with two curvature compensation techniques are presented. The reference achieves a maximum inaccuracy of ±0.2% and a minimum temp-co of 6 ppm/°C from −45°C to 125°C. Furthermore, its temp-co is digitally programmable between −7 mV/100°C and +8 mV/100°C. Its line regulation is 0.1%/V, and it occupies 0.078 mm2.

This paper presents a MUlti-SEnsor biomedical IC (MUSEIC). It features a high-performance, low-power analog front-end (AFE) and fully integrated DSP. The AFE has three biopotential readouts, one bio-impedance readout, and support for general-purpose analog sensors The biopotential readout channels can handle large differential electrode offsets ( ${\pm} $ 400 mV), achieve high input impedance ( ${>}$ 500 M $\Omega$ ), low noise ( ${ 620 nVrms in 150 Hz), and large CMRR ( ${>}$ 110 dB) without relying on trimming while consuming only 31 $\mu$ W/channel. In addition, fully integrated real-time motion artifact reduction, based on simultaneous electrode-tissue impedance measurement, with feedback to the analog domain is supported. The bio-impedance readout with pseudo-sine current generator achieves a resolution of 9.8 m $\Omega$ / $\surd$ Hz while consuming just 58 $\mu$ W/channel. The DSP has a general purpose ARM Cortex M0 processor and an HW accelerator optimized for energy-efficient execution of various biomedical signal processing algorithms achieving 10 $\times$ or more energy savings in vector multiply-accumulate executions.

We present an ultra low power (200 nA current consumption) reverse bandgap voltage reference operational from supply voltages down to 0.75 V. The reference is a part of microprocessor system on chip implemented in a digital 130 nm CMOS process and has a total area of 0.07 mm2. The reference accuracy is ± 2.5% (5 sigma) over a temperature range of - 20 to 85°C without trimming. With trimming ± 0.5% accuracy is achieved.

This paper presents a power-efficient current-feedback instrumentation amplifier (CFIA) with high gain accuracy. It is intended for interfacing precision bridge transducers and thermocouples that output mV-level signals. The gain accuracy of the CFIA is mainly limited by the mismatch of two transconductors. Applying dynamic element matching (DEM) to them ensures good gain accuracy, gain drift, and linearity. As a result, these transconductors can be implemented as simple differential pairs, resulting in significantly improved power efficiency when compared with the use of resistor-degenerated stages. To suppress the output ripple caused by DEM, an automatic gain error reduction loop dynamically nulls the Gm mismatch of the input and feedback transconductors, thus eliminating the need for trimming. The prototype chip was realized in a 0.7-μm CMOS process. Measurement results show a maximum 0.06% untrimmed gain error and a 5-ppm INL at a gain of 100. This work also achieves an NEF of 11.2, a maximum input-referred offset of 3 μV, and a CMRR of 127 dB while consuming only 290 μA at a 5-V supply.

A MOS-input operational amplifier has a reconfigurable input stage that enables trimming of both offset and offset drift based only on single-temperature measurements. The input stage consists of a MOS differential pair, whose offset drift is predicted from offset voltage measurements made at well-defined bias currents. A theoretical motivation for this approach is presented and validated experimentally by characterizing the offset of pairs of discrete MOS transistors as a function of bias current and temperature. An opamp using the proposed single-temperature trimming technique has been designed and fabricated in a 0.5 μm BiCMOS process. After single-temperature trimming, it achieves a maximum offset of ± 30 μV and an offset drift of 0.33 μV/°C (3σ) over the temperature range of -40°C to +125°C.

A phase-alignment system is used in the first reported IC to fully integrate a power amplifier, Cartesian feedback linearization circuitry, and a phase-alignment system. The phase-alignment system consumes 8.8 mW from a 2.5-V supply and employs a new technique for offset-free analog multiplication that enables it to function without manual trimming. Phase alignment of better than 9/spl deg/ is maintained for drifts as large as /spl plusmn/90/spl deg/. We demonstrate how the phase-alignment system improves the stability margins of the fully integrated Cartesian feedback system. The power amplifier itself, integrated on the same die, operates at 2 GHz and delivers a maximum of 14.2 dBm of output power into a 50-/spl Omega/ load. The IC was fabricated in a 0.25-/spl mu/m CMOS process.

Describes a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog converter (DAC) fabricated in 0.25- and 0.18-/spl mu/m CMOS logic processes. We trim the static integral nonlinearity to /spl plusmn/0.3 least significant bits using analog charge stored on floating-gate pFETs. The DAC occupies 0.44mm/sup 2/ of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves better than 72-dB spur-free dynamic range at 250 MS/s.

This paper presents an in-depth treatment of mixers and polyphase filters, and how they are used in rejecting the image in transmitters and receivers. A powerful phasor-based analysis is used to explain all common image-reject topologies and their limitations, and it is shown how this can replace complex trigonometric equations commonly found in the literature. Practical problems in design and layout that limit the performance of image-reject upconversion and downconversion mixers are identified, and solutions are presented or limits explained. This understanding is put to work in a low-IF CMOS wideband, low-IF downconversion circuit, which repeatedly rejects the image by 60 dB over the wide band of 3.5 to 20 MHz without trimming or calibration.

This paper describes a 14-b analog-to-digital converter designed in a complementary bipolar process. Although it uses a fairly traditional three-stage subranging architecture, several nontraditional techniques are incorporated to achieve 14 bits of performance at a clock rate of 100 MHz. For linearity, the most critical of these is wafer level trimming of the first subrange digital-to-analog converter. Prototype silicon exhibits a spurious-free dynamic range of 90 dB through the Nyquist frequency and a signal-to noise ratio of 74 dB while dissipating 1.25 W.

Two key concepts of pipelining and background offset trimming are applied to demonstrate a 13-b 40-MSamples/s CMOS analog-to-digital converter (ADC) based on the basic folding and interpolation architecture. Folding amplifier stages made of simple differential pairs are pipelined using distributed interstage track-and-holders. Background offset trimming implemented with a highly oversampling delta-sigma modulator enhances the resolution of the CMOS folders beyond 12 bits. The background offset trimming circuit continuously measures and adjusts the offsets of the folding amplifiers without interfering with the normal operation. The prototype system is further refined using subranging and digital correction, and exhibits a spurious-free dynamic range (SFDR) of 82 dB at 40 MSamples/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are about /spl plusmn/0.5 and /spl plusmn/2.0 LSB, respectively. The chip fabricated in 0.5-/spl mu/m CMOS occupies 8.7 mm/sup 2/ and consumes 800 mW at 5 V.

A MOSFET-only 10-bit A/D converter is described which achieves a total harmonic distortion of up to -79 dB without trimming or calibration. The maximum conversion rate is 200 ksample/s. Implemented in a 1-/spl mu/m single-poly technology, it occupies 5.12 mm/sup 2/ and consumes 12 mW from a single 5 V supply. The MOSFET-only R-2R ladder, which is the center of the successive approximation architecture, is analyzed, and design considerations, especially the device dimensions, are given. Measurements of the linear behavior of pure MOSFET ladders are presented. The offset sensitivity of the ladder is examined, and an alternative way of summing the ladder current is suggested. A fast and effective differential current comparator is described.

The presented IC performs the high-voltage functions of an electronic central office subscriber line interface without the need for any transformers or relays. The challenges of subscriber line interface circuit (SLIC) integration stem from the combination of conflicting requirements: low impedance line feeding in a 150-V range, current sensing with 0.2% relative accuracy, and stability up to 200 nF loads, while operating in the harsh environment of the telephone line. The newly developed BiCMOS/DMOS process 170-V smart power technology (SPT 170) together with circuit techniques that strongly emphasize the physical device properties (e.g., buffers with DMOS outputs, n-type supply voltage switch, accuracy by polyresistors) yielded a very robust 30 mm/sup 2/ SLIC. All transmission specifications are met without trimming.

A new offset-trimming bit-line sensing scheme is described which is suitable for gigabit-scale DRAM's. This sensing scheme can suppress the sensitivity degradation caused by the large electrical parameter variation of deep submicron transistors. The effective offset voltage dependence on trimming time is analyzed and verified with simulation results. As compared with a conventional direct sensing scheme, the proposed scheme shows remarkable improvement on the sensitivity. A test device was fabricated with a 0.25 /spl mu/m CMOS technology and its measurement results indicate the successful operation of offset-trimming.

The design of an integrated quadrature modulator for a 800-MHz to 1-GHz frequency range is presented. It is shown that this modulator achieves a phase error of less than +or-3 degrees without any trimming or tuning. This performance was achieved by reducing the number of building blocks and keeping a symmetrical transistor structure even in the layout. To overcome the amplitude difference of the phase-shifted signals, a modulator principle is used rather than a multiplier principle. The circuit was implemented in a bipolar transistor array with an f/sub T/ of 9 GHz. >

A subscriber line interface circuit (SLIC) two-chip set that eliminates off-chip functional trimming and integrates coin telephone set facilities as well as BORSCHT functions is described. The LSI chip set consists of (a) a subscriber interface IC fabricated using a 320-V dielectrically isolated bipolar process with on-chip thin-film resistors and double-layer metal, and (b) a subscriber processor IC with oversampling A-D/D-A converters and a microprogrammable digital signal processor (DSP), using a 1.6- mu m CMOS process. Chip sizes are 5.5 mm*6.06 mm and 6.0 mm*5.7 mm, respectively. Using the two-chip set, an SLIC for a coin telephone set can be designed without using high-precision filter components or hybrid ICs with functional trimming. >

The application of floating-gate elements as adjustable components in analog CMOS circuits such as amplifiers is proposed. A simple trimming circuit based on this principle and delivering a differential current is described. Experimental results of a differential difference amplifier (DDA) containing two such circuits are given. After trimming, an offset voltage of 10 mu V and a nonlinearity of 0.1% are achieved. Other analog circuits based on floating-gate elements like adjustable voltage sources and transconductances have been realized. Because they can be electrically reprogrammed, a wide range of applications, for example in neural nets, are possible. >

A family of 8-, 10-, and 12-bit monolithic digital-to-analog converters have been developed which represent the state of the art in high-speed data conversion. Total through-delay plus settling times have been measured at 5 ns for the 8-bit device, 12 ns for the 10-bit, and 45 ns for the 12-bit, the latter still at an experimental stage. All devices are produced by a standard high-speed digital bipolar process without the need for post-process trimming.

An electrical trimming technique for a heavily doped polysilicon resistor (DOT) has been successfully applied to the fabrication of a monolithic 14-bit D/A converter. The converter trimmed by DOT showed a nonlinearity error of less than 1/4 LSB, which means the converter substantially has 15-bit accuracy. Resistance post-trimming stability is greatly improved by introducing an excess trimming and restoration process in DOT, resulting in the achievement of a resistance stability of within /spl plusmn/0.01% of 100 years use at 100/spl deg/C.

A temperature-compensated current reference for CMOS integrated circuits based on a MOSFET as current-defining element, is described. To minimize the mass-production cost, it uses no external components nor trimming procedures. Comparison with classical current references with a resistor as a current-defining element shows a considerable improvement of the relative tolerance on the current. Theoretical expressions are presented and compared with experimental results from an integrated prototype. For devices from the same batch, the standard deviation is measured to be 2.5%, and the temperature dependence is 3% from 0 to 80 degrees C. From theoretical equations, the standard deviation of devices from different batches is expected to be about 15%. >

The development of a new laser-trim technique is described. Metal links, which are arranged to provide incremental adjustments to critical circuit parameters, are cut by a laser. Trimming operations are monitored and controlled by means of a computer program. A comparison is made between currently used trimming methods. An application, to improve the linearity of a 10-bit D/A converter, is described. This trimming technique, which is implemented so that its effects track temperature and reference current variations, allows the converter to be adjusted for better than /spl plusmn/0.05 percent linearity by appropriately modifying the ladder termination voltages.

Describes a monolithic 14-bit DAC which uses a new compensation technique for the DAC linearity, the `self-compensation technique', originated through a new concept. Since this technique automatically compensates for linearity error in the DAC by referring to a ramp function with about 17-bit linearity, a high precision DAC can be produced in monolithic form without the trimming of analog components. An experimental 14-bit DAC chip has been fabricated using analog compatible IIL technology and two-level metalization. A linearity error of less that /spl plusmn/1/2 LSB and a settling time of 1-2 /spl mu/s has been achieved.

An 8-bit resolution ultrahigh-speed monolithic digital-to-analog converter (DAC) is fabricated using super self-aligned process technology. In order to improve dynamic accuracy, which is determined by settling speed, clock feedthrough noise, and glitch, a number of circuit technologies are developed including a rise- and fall-time control switch driver, a low-noise flip-flop, and a differential buffer configuration. In addition, a chip assembly technology using a multilayer ceramic substrate is developed. The DAC exhibits a settling time to 8-bit accuracy of about 2 ns, a maximum conversion rate of 1 GHz, a glitch energy of 2 ps-V, and a 10-bit linearity error accuracy without trimming. >

A floating-gate MOS analog memory circuit that can be electrically programmed for positive and negative voltage changes and that can be fabricated in a standard CMOS IC process is described. Unlike existing electrically erasable floating-gate memory circuits, this circuit does not require special fabrication techniques like ultrathin tunneling oxides or textured polysilicon. Instead, mask geometry is used to cause field-enhanced Fowler-Nordheim tunneling of electrons from a floating gate. Retention measurements at elevated temperatures indicate that the loss of floating-gate charge should be less than 0.1% over a ten-year period at temperatures below 100 degrees C. One limitation of this structure is that the rate of change of the floating-gate voltage can be quite small (e.g. 10 mV/s). A general trimming circuits, whose novel feature is that any number of trimming circuits can be independently and simultaneously adjusted across an entire IC, has been incorporated into a prototype CMOS op amp to decrease its input offset voltage from 10 mV to less than 0.5 mV. >

A pipelined, 13-bit, 250-ksample/s (ks/s), 5-V, analog-to-digital (A/D) converter has been designed and fabricated in a 3- mu m, CMOS technology. Monotonicity is achieved using a reference-feedforward correction technique instead of (self-) calibration of trimming to minimize the overall cost. The prototype converter requires 3400 mil/sup 2/, and consumes 15 mW. >

A monolithic integrated circuit which provides an output voltage scaled proportionally to the Fahrenheit temperature without requiring the user to subtract a large constant offset is described. An advantage of this circuit is that the gain is inherently calibrated (e.g. to /spl plusmn/10.00 mV//spl deg/F) by simply trimming the offset error at room temperature. This behavior is shown to be a predictable function of the inherent bandgap voltage of silicon, +1.220 V. The circuit has been designed to permit trimming of accuracy (gain and offset) by blowing metal links and by the familiar Zener gap technique. The sensor achieves a typical accuracy of /spl plusmn/0.5/spl deg/F at room temperature, and /spl plusmn/1.0/spl deg/F over a rated temperature range from -50/spl deg/F to +300/spl deg/F, without any requirement for laser trimming. The practical limitation on accuracy is the production testing of devices under conditions of precisely known temperature. Applications circuits are also presented to show where this new sensor has advantages in accuracy and convenience over present sensors.

Economical active realizations of low-Q, all-pole, low-pass transfer functions are presented. The realizations allow a unidirectional sequence of functional tuning by trimming only resistors. Also, they have low sensitivities to the passive element variations. Experimental results verified the ease of tuning, the low sensitivity, and the low dependence on temperature and power supply variations.

Describes a 12 bit DAC which uses diffused resistors and requires no trimming to guarantee monotonicity for all grades over the temperature range. The segmented ladder design, departing from the traditional R-2R approach used in virtually all high-speed high resolution converters, provides inherent monotonicity and differential linearity as high as 13 bits. Also afforded is a more uniform step size over the temperature range than the trimmed 12 bit converters. The only critical resistor matching occurs at the major carries or midpoints of each of the eight segments and the tolerances are equivalent to that of a 9 bit DAC, or eight times lower than the R-2H approach. In essence, the problem has been divided into eight separate problems, each with tolerances eight times lower than that of a 12 bit DAC. The converter has been found to be immune to variations in temperature, time, process, and mechanical stress. The circuit also features differential high compliance current outputs, wide supply range, and a multiplying input.

Methods for predicting the performance of laser-trimmed film resistors taking into account the properties of the heat-affected zone (HAZ) are discussed. A figure of merit based upon a sensitivity function called HAZ sensitivity, S/SUP HAZ/, is introduced which is useful for determining aging and temperature effects of an arbitrary film-resistor geometry with an arbitrary trim strategy. S/SUP HAZ/ is also shown to be useful in predicting performance of ratio-matched resistor structures. The proposed technique is incorporated in FIRE, a FORTRAN program for analyzing arbitrary film structures with a given trim path. Examples using popular resistor geometries and trimming algorithms illustrating the use of the suggested figure of merit are presented. The performances of these structures are compared quantitatively.

A technique for permanent adjustment of precision analog circuits at wafer test by selective shorting of Zener diodes is presented. Analytical details of the trimming procedure and a physical description of diode short-circuiting are given. The method is applied to a precision operational amplifier with input offset voltage reduced to 10 /spl mu/V. The necessity of optimizing other related parameters is demonstrated. Practical considerations limiting wafer test accuracy are discussed. Circuit performance is summarized.

An automatic error cancellation technique for higher accuracy successive-approximation analog/digital (A/D) converters is described. The technique uses a binary-weighted capacitor array as its own reference, and no other special elements are required for capacitor mismatch compensation. Experimental results indicate that more than 14-bit A/D conversion can be performed on a conventional MOS IC chip without trimming.