Search

This work addresses the device modeling challenges of production-quality, state-of-the-art, silicon-on-sapphire (SOS) processes. Differences between SOS, silicon-on-insulator (SOI), and bulk CMOS are highlighted, with emphasis on the key differences in the modeling methodology. For RF and low-power applications, SOS has distinct advantages over SOI, such as reduced parasitics, better linearity, and enhanced electrical isolation. Yet little is reported in the literature about modeling of a commercially viable SOS process. Though originally developed for SOI, it is demonstrated that the BSIMSOI model can adequately represent SOS MOSFETs, including fully and partially depleted devices. For RF switch applications, RON and COFF are captured with reasonable accuracy. An additional RF figure of merit, fT, is also reasonably well modeled, yielding peak values in the 40-50 GHz range.

A 150 GHz amplifier in digital 65 nm CMOS process is presented. Matching loss is reduced and bandwidth extended by simplistic topology: no dc-block capacitor, shunt-only tuning and radial stubs for ac ground. Dummy-prefilled microstrip lines, with explicit yet efficient dummy modeling, are used as a compact, density-rule compliant matching element. Transistor layout with parallel gate feed yields 5.7 dB of MSG at 150 GHz. Measurement shows the amplifier exhibits 8.2 dB of gain, 6.3 dBm of Psat, 1.5 dBm of PidB and 27 GHz of 3 dB bandwidth, while consuming 25.5 mW at 1.1 V. The dummy-prefilled microstrip line exhibits QTL ? 12 up to 200 GHz.

This work discusses the design methodologies for efficient power generation at mm-wave frequencies in CMOS. Passive elements play an important role in PA design, as they determine both the output power and power gain of the circuit. In this work, we have developed a methodology for design of transformer-coupled power amplifiers. A distributed model of on-chip transformers has been developed that can predict the performance up to very high frequencies, is length scalable and uses only a few parameters , compared to a complete lumped model. Using the model, a two-stage transformer-coupled PA has been designed in 90 nm CMOS. The prototype has one of the highest output powers reported for a 60 GHz CMOS PA. A three-stage improved design with higher gain and efficiency is reported, stressing the importance of driver stage design at these frequencies. The PA has been integrated into a complete transmitter and tested with 10 Gb/s QPSK modulated data.

The collector current Ic of a bipolar transistor does not instantaneously respond to changes in applied base-emitter voltage Vbe ; its response exhibits a time lag because of the finite transit time of carriers through the transistor, which is manifest as a phase lag (or ldquoexcess phaserdquo) in the frequency domain. In this paper we present an excess phase model that has a constant magnitude response, in contrast to previous models which introduce a change in magnitude as well as in phase, and detail how our model can be implemented in Verilog-A. In addition, we show how a bias dependence of the time lag can be added to the Verilog-A implementation of the Weil-McNamee excess phase model without introducing undesired behavior.

Transmission lines are becoming of common use at mm-wave to implement on-chip functions as impedance matching, filtering and interconnects. Lack of an accurate and fast simulation method is nonetheless evident for transmission lines in scaled CMOS where metal dummies inserted for IC planarization make their physical structure extremely complicate. Although lines are not uniform due to displacement of small dummies, they are still periodic. In this paper, we describe an analytical procedure, leveraging lines periodicity and based on Floquet's theorem, in order to derive electromagnetic parameters from simulations. Conventional, slow-wave and shielded CPWs have been realized in a 65 nm CMOS technology. Thanks to the developed method, an optimum line design has been made possible. The lossy CMOS substrate, responsible for a significant performance degradation, can be effectively shielded and achieved performances are comparable with other technologies considered better suited to implement low-loss, high frequency passive components. Shielded CPW lines show attenuation as low as 0.65 dB/mm at 60 GHz, a record in scaled CMOS.

This paper proposes a simulation-based modeling methodology that provides greater flexibility in the design and layout of millimeter-wave CMOS circuits than measurement- based models do. A physical model for the metallization capacitances of the transistors is described and new layout techniques are introduced that exploit these capacitances to improve the circuit performance. The accuracy of the models is verified by the design and measurement of five oscillators operating in the range of 40 GHz to 130 GHz in 90-nm CMOS technology.

The interaction between substrate and devices is normally neglected during the design of on-chip MOS decoupling capacitors (decaps). However, it may significantly influence the decap performance to reduce high-frequency power supply noise. In this paper we propose a novel six-parameter analytical decap model which accounts for substrate and device interactions. Our model has been compared against state-of-the-art decap models. Moreover, it has been extensively validated through simulations and measurements. For 65 nm LP-CMOS, a close correlation has been obtained over a large frequency range from 10 MHz up to 10 GHz. Furthermore, we introduce the maximum decap admittance as a new metric for decap performance qualification. Closed-form expressions have been derived to calculate maximum admittance. Finally, we determine the relationship between relevant figure-of-merit parameters for decap design optimization.

In this paper, we characterize and model M:N baluns for silicon RFIC design. A modeling methodology is presented based on a geometrically scalable lumped-element approach that incorporates both skin effect and substrate loss. This approach is extended to include the effects of a patterned ground shield under the balun. The modeling approach is validated with measured S-parameters and extracted impedances from various circuit configurations. The impedance transfer characteristics of the model and balun over substrate and over a patterned ground shield are explored. Matching considerations are addressed by evaluating the model accuracy with measured data under matched and unmatched conditions.

The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, control switching power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. With threshold voltage scaling, subthreshold leakage power is expected to become a significant portion of the total power in future CMOS systems. Therefore, it becomes crucial to predict and reduce subthreshold leakage power of such systems. In the first part of this paper, we present a subthreshold leakage power prediction model that takes into account within-die threshold voltage variation. Statistical measurements of 32-bit microprocessors in 0.18-/spl mu/m CMOS confirm that the mean error of the model is 4%. In the second part of this paper, we present the use of stacked devices to reduce system subthreshold leakage power without reducing system performance. A model to predict the scaling nature of this stack effect and verification of the model through statistical device measurements in 0.18-/spl mu/m and 0.13-/spl mu/m are presented. Measurements also demonstrate reduction in threshold voltage variation for stacked devices compared to nonstack devices. Comparison of the stack effect to the use of high threshold voltage or longer channel length devices for subthreshold leakage reduction is also discussed.

In this paper, a distributed capacitance model (DCM) for monolithic spiral inductors is developed to predict the equivalent coupling capacitances C/sub p/ between the two terminals and the equivalent capacitance between the metal track and the substrate C/sub sub/. Therefore, the characteristics of inductors such as the S parameter, the quality factor Q, and the self-resonant frequency f/sub SR/ can be predicted by its series inductance, equivalent capacitances, and series resistance. A large number of inductors have been implemented in 0.25- and 0.35-/spl mu/m CMOS processes to demonstrate the prediction accuracy. For planar and multilayer inductors, DCM can provide a quick and accurate assessment to the design of monolithic spiral inductors.

We give an overview of the state-of-the-art of heterostructure RF-device simulation for industrial application based on III-V compound semiconductors. The work includes a detailed comparison of device simulators and current transport models to be used, and addresses critical modeling issues. Results from two-dimensional hydrodynamic simulations of heterojunction bipolar transistors (HBTs) and high electron mobility transistors (HEMTs) with MINIMOS-NT are presented in good agreement with measured data. The simulation examples are chosen to demonstrate technologically important issues which can be addressed and solved by device simulation.

Reductions in CMOS SRAM cell static noise margin (SNM) due to intrinsic threshold voltage fluctuations in uniformly doped minimum-geometry cell MOSFETs are investigated for the first time using compact physical and stochastic models. Six sigma deviations in SNM due to intrinsic fluctuations alone are projected to exceed the nominal SMM for sub-100-nm CMOS technology generations. These large deviations pose severe barriers to scaling of supply voltage, channel length, and transistor count for conventional 6T SRAM-dominated CMOS ASICs and microprocessors.

This paper reports a MOS transistor mismatch model applicable for submicron CMOS technologies and developed based on the industry standard BSLM3v3 model. A simple and unified expression was derived to formulate the effect of MOSFET mismatch on drain current variance. A way to quickly estimate the drain current mismatch was also suggested. The model has been integrated into HSPICE, and results obtained from simulation and measurements were compared.

This paper describes a design-oriented scalable macromodel for substrate noise coupling in heavily-doped substrates. The model requires only four parameters which can be readily extracted from a small number of device simulations or measurements. Once these parameters have been determined, the model can be used in design for any spacing between the injection and sensing contacts and for different contact geometries. The scalability of the model with separation and width provides insight into substrate coupling and optimization issues prior to and during the layout phase. The model is validated with measurements from test structures fabricated in a 0.5 /spl mu/m CMOS process. Applications of the model to circuit design are demonstrated with simulation results.

On-chip interconnect delays are becoming an increasingly important factor for high-performance microprocessors. Consequently, critical on-chip wiring must be carefully optimized to reduce and control interconnect delays, and accurate interconnect modeling has become more important. This paper shows the importance of including transmission line effects in interconnect modeling of the on-chip clock distribution of a 400 MHz CMOS microprocessor. Measurements of clock waveforms on the microprocessor showing 30 ps skew were made using an electron beam prober. Waveforms from a test chip are also shown to demonstrate the importance of transmission line effects.

There is much more to modeling for circuit simulation than deriving a set of I(V), and perhaps Q(V), equations and extracting a SPICE MODEL card. Unfortunately, some practical aspects of modeling are often overlooked. This paper details common-sense guidelines for modeling and highlights common modeling problems. Particular emphasis is given on understanding accuracy requirements and numerical requirements, on ensuring that compact models are asymptotically correct, and on highlighting the real goal of modeling for circuit simulation: getting complete models for allowable device layouts working in the CAD system on a designer's desk.

Analytical models on metal-oxide-semiconductor field-effect transistor (MOSFET) scaling and complementary (CMOS) ring oscillator performance developed recently are applied to revisit CMOS design guidelines because those based on the basic long channel model are obsolete. Handy and empirical equations for deep submicrometer MOSFET drain saturation current are developed. The differences between the basic long channel model and the accurate deep submicrometer MOSFET current model are highlighted. Design guidelines on V/sub th/ and V/sub dd/ scaling as well as interconnect loading effects based on the accurate models are presented.

We propose a new analytical model for the switching characteristics of CMOS logics. Our new model, named the Switching Response of CMOS logic by Convolution approach (SRC), can successfully produce the output waveforms under any switching conditions with simple analytical expressions. SRC modeling is a process of transforming CMOS logic into a linear system. This model provides procedures to determine the transfer function and the driving function (input of linear system) of the linear system from given CMOS logic, and then an output waveform, expressed as a third-order equation, is obtained by the convolution of two functions. All parameters in this model are determined in a straightforward manner from given device characteristics and layout geometry without empirical or fitting processes and presimulations. In addition, a delay equation is developed based upon the SRC model. With this delay equation, the delay can be predicted within a few percent differences compared to SPICE simulation results for the wide range of input transition time and output loading capacitance.

A completely integrated 1.8-GHz low-phase-noise voltage-controlled oscillator (VCO) has been realized in a standard silicon digital CMOS process. The design relies heavily on the integrated spiral inductors which have been realized with only two metal layers and without etching. The effects of high-frequency magnetic fields and losses in the heavily doped substrate have been simulated and modeled with finite-element analysis. The achieved phase noise is as low as -116 dBc/Hz at an offset frequency of 600 kHz, at a power consumption of only 6 mW. The VCO is tuned with standard available junction capacitances, resulting in a 250-MHz tuning range.

The recent trends in portable computing technologies have established the need for energy efficient design strategies. To achieve minimum energy design goals, system designers need a technique to accurately model the energy consumption of their design alternatives without performing a full physical design and full-circuit simulation. This paper presents and compares five approaches for modeling the energy consumption of CMOS circuits. These five modeling approaches have been chosen to represent the various levels of model complexity and accuracy found in the current literature. These modeling approaches are applied to the energy consumption of SRAM's to provide examples of their use and to allow for the comparison of their modeling qualities. It was found that a mixed characterization model-using a CV/sup 2/ prediction for digital subsections and fitted simulation results for the analog subsections-is satisfactory (within /spl plusmn/1 process variation) for predicting the absolute energy consumed per cycle. This same model is also very good (within 2%) for predicting an optimum organization for the internal structures of the SRAM. Several common architectures and circuit designs for SRAM's are analyzed with these models. This analysis shows that global, rather than local improvements, produce the largest energy savings. >

A method to accurately calculate the delay and the output transition-time of a CMOS inverter for any input ramp and output loading is considered. This paper is an extension of Sakurai's work (1990) on delay modeling of inverters for fast input ramps. We observed that two different mechanisms, that can be adequately modeled analytically, govern the delay and the output transition-time of an inverter in two extreme cases: infinitely fast and infinitely slow inputs. These extreme points are joined by a curve that can predict the delay and the output transition-time for any input. We found that the delay and the output transition-time for an inverter with small fanouts are similar to those for large input transition-times. This behavior is explained by the use of I-V trajectories. We describe a method to generate parameters to model delay and output transition-time for different fanouts and input transition-times; this method can be generalized to add parameters for different temperatures and supply voltages. Given a new process technology and its corresponding SPICE-model parameters, our delay calculation scheme comprises characterizing a minimal number of coefficients for each new technology (a one-time process) and evaluating the analytical forms thereafter to obtain the delay and the transition-time. Our delay equations also explain negative delays that arise in case of slow input rise-times. A program incorporating the above idea has been implemented in C. Delay and transition-time values obtained from the program have been found to be typically within 3% of SPICE. >

The necessary reduction in supply voltage for future scaled-down BiCMOS technologies will cause a degradation in speed because the base-emitter forward voltage drop is not scaled. The analysis of how the performance difference between BiCMOS and CMOS changes with scaling has been ambiguous in previous work because of insufficient model accuracy. In this work, mixed-level device-circuit simulation with accurate numerical device models, used to predict gate delay, output voltage drop, breakdown voltage and hot-carrier reliability estimates for BiCMOS and CMOS structures with different scaling, is described. A very significant result was that for 0.25- mu m feature size the bipolar part of BiCMOS will still contribute to performance if the fan-out is high and if appropriate scaling including doping, supply voltage, vertical dimensions, and lateral dimensions is used. >

A high-speed digital neural network chip adopts a polyhedric discrimination neuron (PDN) model and low-power chain-reaction (LCR) architecture that can reduce the power dissipation to one-fiftieth or less. The chip contains 832 fully implemented digital synapse units that form 13 neurons on a 10.3-mm*14.1-mm die using 0.8- mu m CMOS technology. The synapse weights are updated using an external computer. A computational speed of 8 billion connections per second (GCPS) is achieved with low 54-mW power dissipation. The forward propagation time is 104 ns. These features make it possible to implement large-scale neural network chips and systems. >

A technique for designing totally self-checking FCMOS circuits is presented. Two types of defects have been considered: breaks (caused by missing conducting material or extra insulating material) and transistor stuck-on faults. In order to make FCMOS circuits totally self-checking for all breaks and transistor stuck-on faults, only four extra transistors need to be added to the functional circuit. The additional circuitry is added in such a way that for any break or transistor stuck-on defect in the functional circuit, the outputs assume a value of 01 or 10, respectively. The output of the defect-free circuit will be 11 (00) when the input pattern applied to the circuit connects V/sub dd/(GND) to the output node. >

A CMOS circuit that emulates the FitzHugh-Nagumo neuron model is introduced. A complete derivation of the neuron model is presented, starting with the description of the fundamental biological mechanisms involved in the living neural cell, followed by the mathematical model formulation extracted from these mechanisms. A circuit theory technique for obtaining a physical IC suitable circuit that emulates the derived mathematical equations is then presented, culminating with the presentation of experimental results on a chip fabricated in a 2- mu m double-metal, double-poly CMOS process. It is emphasized that the FitzHugh-Nagumo model is very adequate for emulation of small biological systems. A reduced-complexity oscillatory model suitable for implementation of relatively large neural network architectures is also introduced with several corresponding CMOS realizations and measured results. >

In order to derive analytical delay expressions for CMOS gates in the submicrometer region, a realistic MOS model which incorporates an nth power law MOS model is developed. Closed-form delay formulas are obtained for CMOS inverters and series-connected MOSFET structures (SCMSs) that include short-channel effects. It is shown that the ratio of the delay of NAND/NOR to the delay of the inverter becomes smaller in the submicrometer region, because the V/sub DS/ and V/sub GS/ of each MOSFET in the SCMS are smaller than those of an inverter MOSFET. The smaller voltages in turn mitigate and relax the severe carrier velocity saturation in miniaturized MOSFETs. The results of the analysis for submicrometer VLSI designs show that if the maximum number of series-connected MOSFETs is considered to be five in 2- mu m designs, then the number can be increased to six or seven in the submicrometer circuit design. In typical cases in VLSI designs, the delay ratio for N-SCMS is much less than N/sup 2/. The delay dependence on input terminal position for SCMS structures is also described. >

Four different adders were implemented using a CMOS differential logic, enable/disable differential CMOS logic (ECDL). The authors discuss the design and implementation of several common addition algorithms using ECDL. These adders have the self-timed characteristic. Comparisons are made among these algorithms in terms of delay and area. The actual implementation was done with MOSIS 3- mu m scalable process. Evaluations are performed in terms of area and delay. One conclusion that can be made is that the carry-skip adder seems to have the best speed/area combined performance. A first-order modeling method is used to estimate the area and speed of different implementations. >

Static latchup in CMOS devices placed on a thin epitaxial layer for high-voltage integrated circuits (HVIC) is investigated using SPICE. The layout configuration and substrate current have a major influence on CMOS latchup as compared with conventional CMOS structures. Special latchup conditions exist for NMOS devices adjacent to high-voltage devices due to an extra p-n-p-n path. The results suggest that the use of PMOS adjacent to the high-voltage is best suited, in terms of layout, to avoiding latchup conditions. It is also shown that the latchup of CMOS devices is improved by placing them in an n/sup -/ epitaxial layer on a p/sup -/ substrate. >

Jaeger's buffer comprises a string of tapered inverters. Each inverter is molded by a capacitor and a conductor. In this work, the capacitor is split into inherent and load components (C/sub x/ and C/sub y/), and it is shown that the value of the optimal taper depends on the C/sub x//C/sub y/ ratio: the best taper exceeds Jaeger's 2.72 slope, but only moderately. >

It is shown that some current and proposed SPICE models for MOS thermal noise are inconsistent, either when moving from one operating region to another or when changing model levels. A different model is shown to be consistent with theory in all regions and with all SPICE model levels. The reasons for the inconsistency are explored. >

Driver stages in MOS circuitry have been extensively investigated during the last decade. recently a tapering rule for CMOS buffers was derived showing that the tapering factor ( beta ) is determined by the ratio of output to input capacitance. The derivation fails to account for the correlation between the short-circuit current and beta . As a result, the derived formula consistently overpredicts the value of optimum beta , especially for large input/output capacitance ratios. The authors present a modified formula and a method to account for the effect of the short-circuit current that is viable for buffer stages over a wide range of output/input capacitance ratios; this newly derived formula accurately predicts the optimum tapering factors for BiCMOS as well as CMOS buffer chains. >

A linear model for three high-frequency transistors is presented. The model shows good agreement between measured and simulated Y-parameters at different collector currents for all the three transistors.

The static heat-flow problem has been solved analytically in three dimensions for a two-blocks structure. The computer program calculating the temperature maps is simple and fast. Examples are given of temperature profiles on the chip surface of a high-power IC.

RELIANT, as a CAD (computer-aided design) tool that predicts the failure rate of integrated circuit conductors, is presented. A circuit layout, device models, and process-dependent reliability data are inputs to RELIANT. The interconnect patterns, in a Caltech Intermediate Format (CIF) mask description file, are fractured into a number of characteristic segment types. An equivalent circuit for the interconnect topology is extracted and used in conjunction with SPICE to determine the transient currents in each segment. Using parametric models for electromigration damage, the failure rate of the system is computed, as a function of time. The reliability models are calibrated using lifetime measurements performed on a set of conductor test structures. RELIANT provides designers with feedback on the reliability hazards of a design. Results show the application of the tool to a standard-cell CMOS component. For modeling large VLSI interconnect systems, the incorporation of a switched-level simulator for determining approximate current waveforms is discussed. >

For the purpose of statistical modeling it is necessary to choose a few independent device parameters. A number of devices are characterized in terms of their Gummel-Poon model parameters. Correlations between these parameters are studied. The parameters are divided into two groups. The first group consists of parameters depending on collector doping. Collector resistance R/SUB C/ can be chosen as the controlling parameter for this group. The second group comprises the parameters influenced by emitter and base dopings. For this group, using the statistical method of factor analysis to analyze these correlations, it is shown that the variation in the measured data can be effectively expressed in terms of only a few controlling parameters. It is shown that the saturation current I/SUB S/ shows good correlations with most of the model parameters and can be used as an independent parameter from which other parameters can then be computed.

This paper discusses the use of ion implantation to develop a viable high-yielding process for fabricating super-gain transistors for integrated circuits. The authors discuss the fabrication processes utilized, the pertinent device physics, the manufacturing tradeoffs, and present the results obtained for two different ion-implanted base integrated-circuit processes.

A testable design of a CMOS synchronous counter is presented with test vectors that provide 100% coverage of stuck-at and stuck-open faults in a time of order L/sup 2/, where L is the bit length of the counter. This design is made compatible with the scan design methodology by incurring minimal hardware overhead which is also fully testable for the above faults. Test application time is shown to be strongly dependent on observability of the counter outputs and can be considerably reduced if the outputs are directly observable without having to scan the test results out. The authors develop a signal flow model for the counter, based on which, test vectors are derived and proved to provide complete coverage of the above faults. The design is also superior in that its operating speed is only limited by a single inverter delay, found to be 1-4 ns per bit slice, depending on the CMOS process. Furthermore, this speed is not affected by the addition of scan circuitry. >

A large-signal model is derived for the substrate fed integrated injection logic (I/SUP 2/L) gate which is suitable for computer-aided circuit design and the optimization of the physical structure. Since the analysis extends the Ebers-Moll model it differs from the existing models in that the effects of high-level injection and injector debiasing are included. Furthermore, heavy doping effects are included in the calculation of currents and minority carrier storage. The analysis of the oxide isolated structure predicts circuit delays of less than 5 ns at 50 /spl mu/A.

High-voltage double diffused metal-oxide semiconductor transistors (DMOST's) have been fabricated with drain-source breakdown voltage greater than 200 V. This paper describes an experimental and theoretical study of the current-voltage behavior of these devices leading to a two-component MOS field effect transistor (MOSFET)-resistor model appropriate for computer-aided circuit design. The effects of velocity saturation, mobility reduction, and nonuniform impurity concentration in the channel, and of spreading resistance in the drift region are considered. Parameter extraction for experimentally characterizing these effects is described. Comparison of experimental and theoretical results shows that the model accurately predicts the device I/V characteristics. The range of validity of the model is limited primarily by high current saturation effects.