Search

A CMOS bone-guided cochlear implant (BGCI) microsystem is proposed and verified. In the implanted System on Chip (SoC) of the proposed BGCI, the evoked compound action potential (ECAP) acquisition and electrode–tissue impedance measurement (EAEIM) circuit is integrated to measure both ECAP and electrode–tissue impedance for clinical diagnoses. Both positive-/negative-voltage charge pumps and monopolar biphasic constant-current stimulation (CCS) stimulator are designed on-chip to realize monopolar biphasic CCS or double-electrode multiple stimulations with a maximum stimulation current of 1.2 mA and a step of 10 $\mu \text{A}$ . With the double-electrode multiple stimulations, the electric field can be shifted and localized under the stimulating electrode to stimulate the auditory nerves. The wireless bilateral data telemetry circuits with a full-wave active rectifier and the pulsed load-shift keying (PLSK) modulators/demodulators are designed for power and data transmission. In vivo animal tests on guinea pigs have shown that the Wave III of electrically evoked auditory brainstem responses (EABRs) can be evoked successfully by electrical stimulation. Moreover, the decreasing latency gradient of evoked Wave III has been measured under the double-electrode multiple stimulations where the location of peak electric field can be shifted to the stimulating electrode in the apical site to stimulate the auditory nerves. Thus, the desired frequency resolution and spatial specificity of stimulation can be achieved. Both electrical measurement and in vivo animal tests have verified that the proposed BGCI microsystem is a feasible solution to eliminate the symptoms for patients with high-frequency hearing loss.

This article presents a fully energy-autonomous temperature-to-time converter (TTC), entirely powered up by a triboelectric nanogenerator (TENG) for biomedical applications. Existing sensing systems either consume too much power to be sustained by energy harvesting or have poor accuracy. Also, the harvesting of low-frequency energy input has been challenging due to high reverse leakage of a rectifier. The proposed dynamic leakage suppression full-bridge rectifier (DLS-FBR) reduces the reverse leakage current by more than 1000 $\times $ , enabling harvesting from sparse and sporadic energy sources; this enables the TTC to function with a TENG as the sole power source operating at $\mu \text{m}$ 1P6M CMOS technology, consuming 0.14 pJ/conversion with 0.014-ms conversion time.

This article presents a 6.78-MHz single-stage dual-output regulating rectifier for miniaturizing the true wireless devices. The proposed rectifier topology realizes ac–dc power conversion and dual-output voltage regulation simultaneously in one single stage, using only four on-chip power transistors, thereby reducing chip area and off-chip components and improving the system power conversion efficiency. We integrate high voltage (HV) and low voltage (LV) transistors in the proposed dual-output rectifier for HV and LV output voltages, respectively. The proposed two independent three-level current-wave modulation (CWM) controllers realize voltage conversion and regulation for each output independently, with the instant transient response and no cross-regulation problem. The proposed dual-output regulating rectifier, fabricated in 0.18- $\mu \text{m}$ CMOS using 1.8-/3.3-V devices, can deliver a total maximum power of 1.02 W at the dual-output voltages of 1.8 and 3.3 V. The circuit achieves a measured peak efficiency of 91.9% with an instant load-transient response for a load current step between 20 and 200 mA. The cross-regulation between the dual-output voltages is unnoticeable.

This article presents a 6.78-MHz wireless power transfer system with a structure-reconfigurable power amplifier (SR-PA) and a 0X/1X regulating rectifier. The proposed 0X/1X regulating rectifier with local-loop control achieves voltage rectification and regulation without dc–dc converter usage to improve the receiver efficiency. To further enhance the system efficiency, the proposed SR-PA with global-loop power control adjusts its power-stage structure to realize adaptive power delivery. The transmitter and receiver chips were fabricated in a 0.25- $\mu \text{m}$ CMOS process using 5-V devices, and the resulting system was able to regulate an output voltage of 5 V. The measurement results demonstrated an 11.2% improvement in system efficiency for a light load and a 2.7 times increase in available output power compared with the same system without transmission power control. A measured peak receiver efficiency of 92.9% and a total system efficiency of 71.5% were also demonstrated.

Tiny implantable medical devices in millimeter size demand advanced wireless power solutions that operate at hundreds of megahertz and mainly use passive rectifiers for ac–dc power conversion. A conventional cross-connected (CC) rectifier can operate with high frequency and low input voltage but only achieves good efficiencies in a very narrow input power range, due to the shoot-through and reverse currents. This work presents a CMOS passive rectifier with active bias tuning (ABT), allowing a widely extended input range with high power conversion efficiency (PCE). In addition, we compensate for the process, voltage, and temperature variations with the ABT scheme that leads to a robust design for very-high-frequency (VHF) operation. Meanwhile, we propose a peak $V_{\mathrm {OUT}}$ searching scheme to indicate the charging/discharging directions for the ABT. We obtain a bias-voltage balancing among stacked rectifier stages with a switched-capacitor network. The proposed rectifier is fabricated in a 65-nm CMOS process. Measurement results of three chips show that the proposed rectifier improves the PCE over a wide input range, with an average maximum PCE of 64.4%.

This article proposes a split-phase flipping-capacitor rectifier (SPFCR) to resolve the hard tradeoff between the number of capacitors and the energy-extraction efficiency for capacitive piezoelectric energy-harvesting (PEH) interfaces. By splitting the capacitor usage into multiple phases, this article can achieve the most number of flipping phases using the same number of capacitors when compared with the state of the art. We also relaxed the implementation complexity by removing insignificant SFPCR flipping phases without sacrificing the energy-harvesting efficiency. To improve further the input power adaptation, the flipping capacitors are reconfigured as a multiple-voltage-conversion-ratio (MVCR) switched-capacitor dc–dc converter during the non-flipping period without using extra passives. Maximum-power-point tracking (MPPT) is also accomplished using the full-bridge rectifier (FBR) fractional open-circuit voltage ( $V_{{\text {OC}, \text {FBR}}}$ ) to relax the voltage-tolerance requirements. Fabricated in 0.18- $\mu \text{m}$ CMOS, the proposed 21-phase SPFCR PEH interface demonstrates a measured maximum output power improving rate (MOPIR) of up to 9.3 $\times $ with $V_{D}= 0.12$ V (6.5 $\times $ with $V_{D}= 0$ V) when compared with the conventional FBR interface over an equivalent FBR input power range ( $P_{{\text {in, FBR}}}$ ) from 0.15 to 5.57 $\mu \text{W}$ .

This article presents a novel architecture for realizing the synchronized-switch-harvesting-on-capacitors (SSHC) technique used for enhanced energy extraction from piezoelectric transducers. The proposed architecture allows full integration by utilizing the storage capacitor already present in most energy-harvesting systems. A promising circuit implementation of the technique, named multilevel SSHC (ML-SSHC), is proposed as well, and its performance is analyzed theoretically. Based on that, a fully integrated and power-efficient transistor-level design in 0.18- $\mu \text{m}$ CMOS is presented and fabricated in a prototype chip. When operating at a mechanical excitation frequency of 22 Hz and delivering between 1.51 $\mu \text{m}$ and 4.82 $\mu \text{W}$ , the measured increase in extracted power is $7.01\times $ and $6.71\times $ , respectively, relative to an ideal full-bridge rectifier. While the performance is comparable to the state of the art, this is the first implementation allowing full integration at such low frequencies without posing special requirements on the piezoelectric harvester.

This article presents a high-voltage (HV) dual-input (DI) buck converter for triboelectric (TE) energy-harvesting applications with a maximum power point tracking (MPPT) for TE nanogenerators (TENGs). An important characteristic of TENGs is their ac output voltage with different positive and negative peak voltages; thus, the proposed system separately harvests each half-wave (HW) with a dual-output rectifier for better extraction efficiency. Furthermore, given the similarity between the electrical models of piezoelectric transducers and TENGs, a root-mean-square MPP analysis is proposed with a fractional open-circuit voltage (FOCV) method according to each HW from the TENGs. The HV DI buck converter regulates two HVs from the TENGs for MPPT with a single inductor. The proposed HV protector prevents the breakdown of the power transistor due to HV stress. To regulate the two input voltages of the buck converter at each MPP, a synchronous pulse-skipping modulation technique is implemented in the system. The entire system is fabricated in a 180-nm BCDMOS process with an active area of 2.482 mm2. The maximum input voltage of the HV DI buck converter is 70 V, and the maximum end-to-end efficiency of 52.90% is achieved with human skin-based and polytetrafluoroethylene-based TENGs.

A 6.78-MHz fully integrated single-stage wireless charger with constant-current constant-voltage (CC-CV) charging technique for resonant wireless power transfer applications is presented. Based on the principle of three-mode reconfigurable resonant regulating ( $R^{3}$ ) rectifier, the proposed charger achieves high efficiency and low cost by realizing power rectification, voltage regulation, and CC-CV charging in a single power stage. The power stage of the proposed charger consists of only four nMOS power transistors. A bootstrapping technique using a single-input-dual-output voltage doubler with adaptive phase control is also proposed to integrate bootstrap capacitors on-chip. The CC loop and the CV loop share the same pulsewidth modulation (PWM) controller with smooth transition from the CC mode to the CV mode. An on-chip current sensing and estimation circuit is specially designed for the CC loop. Fabricated in a standard 0.35- $\mu \text{m}$ CMOS process with a die area of 8 mm2, the charger delivered a maximum charging current of 1.5 A, and the measured peak efficiency reached 92.3% and 91.4% when the charging currents were 1 A and 1.5 A, respectively.

This article presents a novel CMOS active rectifier for the emerging modality of capacitive wireless power transfer to biomedical implants with high power budgets. For operation versatility in terms of the input frequency, output power level, input voltage range, and load value, dual-loop adaptive delay compensation is utilized to provide both high resolution and high dynamic range in switched-offset currents of comparators that can be reconfigured for low- and high-speed operation modes for automatic adaptation to the input frequency. Fabricated in 0.18 $\mu \text{m}$ 1P/6M CMOS, the rectifier features power conversion efficiency (PCE) of >84.4% (peak of 91.5%) and voltage conversion ratio (VCR) of >88.6% (peak of 95.1%) when operating in 1–10 MHz and driving a load of 300 $\Omega $ . Moreover, for a load range of 20 $\Omega $ –1 $\text{k}\Omega $ at 5 MHz, PCE of 81%–91.8% and VCR of 78.4%–95.4% are achieved, with a maximum output power of ~232 mW at 50 $\Omega $ with a PCE of 90.1%. The active rectifier is also interfaced with a series-resonant capacitive link formed with coated flexible copper plates around a 3-mm-thick layer of muscle tissue, demonstrating an end-to-end power transfer efficiency of >40% in 2–10 MHz and with a load of 300 $\Omega $ .

Piezoelectric energy harvesters (PEHs) are widely deployed in many self-sustaining systems, and proper rectifier circuits can significantly improve the energy conversion efficiency and, thus, increase the harvested energy. Various active rectifiers have been proposed in the past decade, such as synchronized switch harvesting on inductor (SSHI) and synchronous electric charge extraction (SECE). This article presents a sense-and-set (SaS) rectifier that achieves maximum-power-point-tracking (MPPT) of PEHs and maintains optimal energy extraction for different input excitation levels and output voltages. The proposed circuit is fabricated in the 0.18- $\mu \text{m}$ CMOS process with a 0.47-mm2 core area, a 230-nW active power, and a 7-nW leakage power. Measured with a commercial PEH device (Mide PPA-1022) at 85- and 60-Hz vibration frequency, the proposed circuit shows 512% and 541% power extraction improvement [figure of merit (FoM)] compared with an ideal full-bridge rectifier (FBR) for ON-resonance and OFF-resonance vibrations, respectively, while maintaining high efficiency across different input levels and PEH parameters.

To overcome the low-efficiency and limited working range of the existing RF energy harvesting (EH) systems for the wireless Internet-of-Things (IoT) sensors, a novel reconfigurable system is proposed with integrated hill-climbing, maximum power point tracking (MPPT) function for wide input power from −22 to 4 dBm. A conceptual linear model with high accuracy is also proposed to analyze the rectifier efficiency for MPPT operations. The rectifier with off-chip matching is designed with a patch antenna at 915-MHz the industrial, scientific and medical (ISM) band. To further improve the end-to-end efficiency, the harvested power is used to power up the circuit block in system on a chip (SoC) directly, avoiding additional conversion loss. Our proposed reconfigurable 12-stage rectifier with matching network achieves −18.1-dBm sensitivity for 1- $\text{M}\Omega $ loading and 36% peak efficiency at 1 dBm. The proposed MPPT function can detect and determine the optimal rectifier stage for loading from 10 $\text{K}\Omega $ to 1 $\text{M}\Omega $ . The measured MPPT accuracy is over 87% from −22 to 4 dBm compared to external tuning conditions. The minimum stand-by power is 20 nW at 0.5 V and the overall MPPT power efficiency is over 72% with a peak value of 99.8% including dissipated power. Measurements also show the system can achieve self-startup and self-sustained functions with a 10- $\mu \text{F}$ external capacitor buffer.

The full-wave rectifier is the most straightforward way of extracting energy from a piezoelectric source. Unfortunately, the inherent capacitance of the piezoelement significantly limits the efficiency of extraction. The bias-flip rectifier, which aims to mitigate this problem, not only needs a large inductor for efficient operation, but also needs the generation of pulses with a precisely defined ontime. A large inductor increases the overall volume of the system. We present the multi-stage bias-flip rectifier, which is a technique that achieves a high voltage-flip efficiency using a much smaller inductor, and relaxes timing-accuracy requirements. The rectifier, implemented in a 130-nm CMOS process, dissipates about 2 $\mu \text{W}$ and achieves a voltage-flip efficiency of 89.5% while using only a 47 $\mu \text{H}$ inductor.

In this paper, an adaptive delay time control (ADTC)-based CMOS active rectifier is proposed. Compared with previous active rectifiers, power-hungry comparators are eliminated in this structure. Instead, optimal on/off time of the power switches is generated by two current controlled delay lines (CCDLs), which enables drastic power reduction of the active rectifier. In addition, the multiple-pulsing problem is eliminated due to the introduced control mechanism. The high-precision on/off control at picosecond-level precision removes the reverse current of the rectifier and guarantees high voltage conversion rate (VCR) and power conversion efficiency (PCE). The active rectifier is fabricated with a standard 0.18- $\mu \text{m}$ CMOS process. The experimental results show that the quiescent power consumption of the rectifier is less than 230 $\mu \text{W}$ . The current conduction angle reaches the optimal state under different input and load conditions because of the adaptive adjustment. The peak PCE is 94.1% at the output power of 10.63 mW. The PCE is enhanced by 6.7% compared with the previous design. The maximum output power of 34.1 mW is achieved with input ac amplitude of 2.5 V. The proposed low-power high-efficiency active rectifier gives a favorable solution for the wireless power transmission systems.

An integrated power management (IPM) with the unique capabilities of seamless-voltage-/current-mode (SVCM) operation and energy recycling is presented for robust inductive power delivery. Utilizing parasitic bulk diodes with lower voltage drop, this IPM seamlessly transitions between voltage mode (VM) and current mode (CM) in a safe and robust fashion, extending the input-voltage range (removing dead zone) and significantly improving power-conversion efficiency (PCE) in CM operation. The IPM first provides the required load power ( $\text{P}_{L}$ ) by one-step rectification/regulation, and then stores the surplus energy into a storage capacitor to extend the receiver (Rx) operation time via energy recycling when the input power is insufficient. The theory behind the energy recycling is presented. A proof-of-concept chip was fabricated in a 0. 35- $\mu \text{m}$ CMOS process. In measurements, the chip safely achieved a regulated voltage of 3 V for a wide input-voltage range (without dead zone) by switching the Rx LC-tank at 142 kHz. With zero input power, the chip extended the Rx operation time by 250% thanks to the energy recycling.

The widespread use of WiFi in the 2.4-GHz ISM band creates the potential for RF powering using WiFi radios. This paper presents the design of a cm-scale RF-energy harvester including antenna, rectifier, and dc–dc boost converter for RF powering in the 2.4-GHz ISM band. The rectifier and boost converter are designed while considering cold-start operation and nanowatt-scale available power from the rectifier for RF incident power $\times $ and ~2 $\times $ improvement in range compared to prior art. Measurements using a commercial WiFi TX demonstrate the ranges of up to 1.25 m for 14-dBm output power with 1.3% TX duty-cycling in WiFi access-point mode, demonstrating the feasibility of powering sensors from RF power beacons in the 2.4-GHz ISM band as well as from background WiFi transmissions.

This paper introduces a fully integrated RF energy-harvesting system. The system can simultaneously deliver the current demanded by external dc loads and store the extra energy in external capacitors, during periods of extra output power. The design is fabricated in 0.18-μm CMOS technology, and the active chip area is 1.08 mm 2 . The proposed self-startup system is reconfigurable with an integrated LC matching network, an RF rectifier, and a power management/controller unit, which consumes 66-157 nW. The required clock generation and the voltage reference circuit are integrated on the same chip. Duty cycle control is used to operate for the low input power that cannot provide the demanded output power. Moreover, the number of stages of the RF rectifier is reconfigurable to increase the efficiency of the available output power. For high available power, a secondary path is activated to charge an external energy storage element. The measured RF input power sensitivity is -14.8 dBm at a 1-V dc output.

Piezoelectric harvesters are capable of generating energy out of ambient vibrations. Dedicated interface circuits can significantly increase the harvesting capabilities compared with passive rectifiers. This paper presents an autonomous piezoelectric energy harvesting system in a 0.35- $\mu \text{m}$ CMOS process. The implemented interface is based on the parallel-SSHI technique and can harvest from periodic and shock excitations. Regular operation is enabled for input voltages as low as 670 mV. It extracts up to 6.81 times more power compared with an ideal full-bridge rectifier depending on the generator characteristics and excitation conditions. The device is capable of cold startup and provides a stable output voltage for powering an application.

In this paper, a near-optimum active rectifier is proposed to achieve well-optimized power conversion efficiency (PCE) and voltage conversion ratio (VCR) under various process, voltage, temperature (PVT) and loading conditions. The near-optimum operation includes: eliminated reverse current loss and maximized conduction time achieved by the proposed sampling-based real-time calibrations with automatic circuit-delay compensation for both on- and off-time of active diodes considering PVT variations; and power stage optimizations with adaptive sizing over a wide loading range. The design is fabricated in TSMC 65 nm process with standard I/O devices. Measurement results show more than 36% and 17% improvement in PCE and VCR, respectively, by the proposed techniques. A peak PCE of 94.8% with an $80~\Omega $ loading, a peak VCR of 98.7% with 1 $\text{k}\Omega $ loading, and a maximum output power of 248.1 mW are achieved with 2.5 V input amplitude.

An adaptive on/off delay-compensation technique is proposed to improve the performance of CMOS active rectifiers for wireless power transfer (WPT) systems. The effects of the on/off delays on the performance of the active rectifiers with either a parallel-resonant or a series-resonant circuit at the secondary coil are studied, which include power conversion efficiency (PCE), voltage conversion ratio (VCR) and output voltage ripple. By adding two feedback loops to the active diodes to generate the switched-offset currents for the comparators adaptively, both on- and off-delays are compensated for accurately against PVT variations and mismatches. As a design example, a fully integrated active rectifier for biomedical applications with a parallel-resonant secondary was fabricated in a standard 0.35 μm CMOS process. With an AC input that ranges from 1.8 to 3.6 V, the measured VCR is higher than 90% and the measured PCE is higher than 89.1% for a load resistor of $500\ \Omega$ . In particular, the PCE is increased by 9% compared to the active rectifier without using the proposed technique.

A piezoelectric (PE) energy harvesting system with one-cycle maximum power point (MPP) sensing is presented. The one-cycle MPP sensing method uses a very small size sensing capacitor and it can make the transducer output voltage reach the open circuit voltage within one cycle. The proposed MPP sensing block can sense the open circuit voltage with a proposed peak detector and stores the MPP voltage using charge sharing blocks. The one-cycle MPP sensing approach simplifies the design of an MPP tracking algorithm and greatly reduces the tracking time. All control blocks are self-biased and choose the higher voltage between the input or output voltages of the switching converter as a supply voltage (V $_{DD}$ ). Therefore, a voltage multiplexer and a low-power ramp generator with V $_{DD}$ independence are also proposed to control the system without additional DC to DC converter. The entire system has been implemented in a 0.35 µm BCDMOS process. It operates at 90 kHz with a 10-mH inductor. The total power dissipation of the controller is 10 µW at a V $_{DD}$ of 2.7 V. The MPP tracking time is only 9.09 ms/V when the input voltage of the switching converter is changed from 3.4 V to 1.2 V.

A 13.56 MHz wireless power transfer system with a 1X/2X reconfigurable resonant regulating (R $^3$ ) rectifier and wireless power control for biomedical implants is presented. Output voltage regulation is achieved through two mechanisms: 1) a local PWM loop at the secondary side controls the duty cycle of mode-switching of the rectifier between the 1X and 2X modes; and 2) a global control loop obtains the mode-switching information from the secondary side and send it back to the primary side through the wireless channel and adjusts the transmitter power of the primary coil to adapt to load and coupling variations. Two novel backscattering uplink techniques are proposed for fast and energy-efficient data feedback. The first is for general data transmission using Manchester code; and the second is for fast duty cycle feedback to cater for fast load-transient responses. Stability analysis of the entire system with the two control loops is also presented. The primary transmitter and the secondary R $^3$ rectifier are fabricated in 0.35 µm CMOS process with the digital control circuits implemented using FPGA. The measured maximum received power and receiver efficiency are 102 mW and 92.6%, respectively. For load transients, the overshoot and the undershoot are approximately 110 mV and the settling times are less than 130 µs.

In this paper, a 13.56 MHz CMOS near-field inductive link power supply (ILPS) that can deliver 20 mA output current for implantable medical devices (IMDs) is proposed and fabricated. In the proposed ILPS, the pair of inductive link coils is constructed in the spiral shape with a ferrite core to save space and increase efficiency. Experimental results have shown that the near-field coils can transmit power at the resonant frequency of 13.56 MHz with the transmission efficiency up to 76.3%. The CMOS power regulator is composed of active voltage doubler rectifier (VD) and low-dropout regulators (LDOs). In the active VD with the comparator, the input offset voltage is adjustable for delay compensation and a start-up control circuit is added to achieve robust start-up mechanism. On-chip delay compensation control with SR-latches is proposed to prevent from error glitch switching on offset voltage control and achieve accurate delay compensation so that the reverse current conduction can be avoided and the efficiency can be increased. Three fully-integrated LDOs with rectifier output voltage of 2 V to 1.8 V are realized for analog (ALDO), digital (DLDO), and reference-voltage (RLDO) circuits. Thus the performance of individual LDO can be optimized. The measured output ripple voltage of the active VD is 10.4 mV. The power conversion efficiency (PCE) is 85% under 20 mA output current. The measured dropout voltage is 384 mV. As compared with other designs, the proposed ILPS has lower ripple voltages, lower dropout voltage, and higher PCE.

In this paper, a design method for the co-design and integration of a CMOS rectifier and small loop antenna is described. In order to improve the sensitivity, the antenna-rectifier interface is analyzed as it plays a crucial role in the co-design optimization. Subsequently, a 5-stage cross-connected differential rectifier with a 7-bit binary-weighted capacitor bank is designed and fabricated in standard 90 nm CMOS technology. The rectifier is brought at resonance with a high-Q loop antenna by means of a control loop that compensates for any variation at the antenna-rectifier interface and passively boosts the antenna voltage to enhance the sensitivity. A complementary MOS diode is proposed to improve the harvester's ability to store and hold energy over a long period of time during which there is insufficient power for rectification. The chip is ESD protected and integrated on a compact loop antenna. Measurements in an anechoic chamber at 868 MHz demonstrate a -27 dBm sensitivity for 1 V output across a capacitive load and 27 meter range for a 1.78 W RF source in an office corridor. The end-to-end power conversion efficiency equals 40% at -17 dBm.

The design of a Resonant Regulating Rectifier (3R) capable of switching-mode operation is presented. The proposed 3R is a highly efficient receiver circuit intended for use in Resonant Wireless Power Transfer (RWPT) application with a 6.78 MHz resonant frequency. Owing to the inductance of resonant coils, the 3R does not require any additional inductor for the switching-mode regulation. The transmitted power via the RWPT with the 3R ranges from 0 W to 6 W, and its peak efficiency reaches 86%. It employs the Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM) for different output power levels. This helps to increase the output power and to lower the voltage stress on the transistor. Fabricated in 0.35 μm BCD technology, the 3R circuit occupies an area of 2.35×2.35 mm2. The functionality of the 3R is successfully demonstrated using a transmitter circuit with resonant coils.

Wireless microsystems like biomedical implants and embedded sensors derive energy from tiny in-package sources that, unfortunately, exhaust easily, which means that operational life is short. Periodically coupling power wirelessly is one way of replenishing onboard batteries, except that small receiver coils suffer from low coupling factors kC and induce low electromotive-force voltages. Today, receivers store and resonate incoming energy between the receiving coil and an off-chip capacitor until the voltage rises sufficiently high for a diode-bridge rectifier to steer power into a battery. The capacitor, however, requires board space and constrains the source to a particular frequency. The 180-nm CMOS power receiver presented in this paper removes the diode bridge, which establishes a minimum voltage below which the system cannot derive power, so that neither tuning nor a resonating capacitor is necessary. Experimental measurements show that the system draws power from 30-mV signals when kC is 0.0046 and coil separation is 11.35 mm, and this threshold voltage only changes 13.6 mV across 100-150 kHz, which is a 27.1% lower threshold voltage that is 36 × less sensitive than its resonating counterpart. The peak efficiency of the receiver when rectifying to 1.2 V is 82% at 224 μW and 125 kHz and average efficiency is 76% for 90-386-mV coil voltages.

A power-efficient wireless stimulating system for a head-mounted deep brain stimulator (DBS) is presented. A new adaptive rectifier generates a variable DC supply voltage from a constant AC power carrier utilizing phase control feedback, while achieving high AC-DC power conversion efficiency (PCE) through active synchronous switching. A current-controlled stimulator adopts closed-loop supply control to automatically adjust the stimulation compliance voltage by detecting stimulation site potentials through a voltage readout channel, and improve the stimulation efficiency. The stimulator also utilizes closed-loop active charge balancing to maintain the residual charge at each site within a safe limit, while receiving the stimulation parameters wirelessly from the amplitude-shift-keyed power carrier. A 4-ch wireless stimulating system prototype was fabricated in a 0.5-μm 3M2P standard CMOS process, occupying 2.25 mm². With 5 V peak AC input at 2 MHz, the adaptive rectifier provides an adjustable DC output between 2.5 V and 4.6 V at 2.8 mA loading, resulting in measured PCE of 72 ~ 87%. The adaptive supply control increases the stimulation efficiency up to 30% higher than a fixed supply voltage to 58 ~ 68%. The prototype wireless stimulating system was verified in vitro.

This paper reports a high-frequency DC-DC boost converter capable of sustaining up to 4× the rated process voltage using high-voltage devices fabricated in standard 0.13 μm 1.2 V CMOS without additional masking steps. Integrated Schottky Barrier Diodes (SBD) and high-voltage stacked composite NMOS switches enable processing of large voltages in a 100 MHz digitally assisted four-phase switched inductor (SI) boost converter architecture. A high-frequency digital delay-locked loop (DDLL) is employed to automatically stagger and synchronize each phase to a primary current-mode pulsed-width modulator (PWM) controller, thus eliminating the need for multiple current sensing circuits. The converter operates in discontinuous conduction mode (DCM) and utilizes integrated Schottky diode output rectifier stages to eliminate dead-time controllers and power hungry high side drivers. The converter operates at 100 MHz with four external 22 nH inductors and achieves an output conversion range of 3 V to 5 V from a 1.2 V input supply. It can deliver 240 mW at 3 V and 200 mW at 5 V with an efficiency of 60%, and ~ 180 mW at 3 V with peak efficiency of 64%.

A 0.025-0.45 W inductive-coupling power transceiver for non-contact memory applications is presented. To deal with sudden and large load variations and achieve high-efficiency, we propose a power transceiver with 5-bit feedforward control. Knowing that load patterns of a memory card have strong correlation with commands issued by a host, feedforward control is applied to minimize response times. To achieve 5-bit power levels, the proposed transceiver utilizes pulse-density modulation (PDM) and a multi-channel structure. Different operation frequencies are chosen for each channel to maximize power transfer efficiency. To further improve transceiver efficiency and enable high-speed operation, an active rectifier with a fast positive feedback is proposed. The test prototype demonstrates 40%-70% efficiency across all load conditions and 60% efficiency in average, which are over an order of magnitude improvements compared to prior arts.

This paper reports on efficient interfacing of typical vibration-driven electromagnetic transducers for micro energy harvesting. For this reason, an adaptive charge pump for dynamic maximum power point tracking is compared with a novel active full-wave rectifier design. For efficient ultra-low voltage rectification, the introduced active diode design uses a common-gate stage in conjunction with supply-independent biasing. While this active rectifier offers low voltage drops, low complexity and ultra-low power consumption, the adaptive charge pump allows dynamic maximum power point tracking with implicit voltage up-conversion. Hence, efficient energy harvesting with high-resistive transducers, e.g., electromagnetic generators, becomes possible even at buffer voltage levels far above actual transducer output voltages. Both interfaces are fully-integrated in a standard 0.35 μm twin-well CMOS process. The designs are optimized for sub-mW transducer power levels and wide supply voltage ranges. Thus, these presented transducer interfaces are particularly suitable for compact micro energy harvesting systems, such as wireless sensor nodes or medical implants. The active diode rectifier achieves efficiencies over 90% at a wide range of input voltage amplitudes of 0.48 V up to 3.3 V. The adaptive charge pump can harvest with a total efficiency of close to 50%, but very independent of the actual buffer voltage. This charge pump starts operating at a supply voltage of 0.8 V, and has an input voltage range of 0.5 V-2.5 V . Finally, results of harvesting from an actual electromagnetic generator prototype are presented.

A 100-V ac energy meter based on the system-on-a-film (SoF) concept, in which various devices are integrated on a flexible film, is presented. The system consists of 20-V organic CMOS digital and analog circuits with a floating gate (FG) for process variation compensation, 100-V organic pMOS rectifiers for generating a 50-Hz clock and 20-V dc power, and an organic LED (OLED) bar indicator. The energy meter based on the SoF is flexible and therefore can be installed to monitor each ac outlet simultaneously. The organic devices are printable, and it is expected that they can be formed using a low-cost printing process in the future. The energy meter can measure the accumulated energy of a 100-Vrms ac lineup to a full-scale value of 360 Wh when a 500-W target load is monitored. The flexible film is foldable and its total area excluding the ac connector is 200 × 200 mm2 in the unfolded form or 70 × 70 mm2 when folded.

This paper reports design, analysis and optimization of a new low-parasitic, very-low-triggering-voltage dual-directional silicon-controlled rectifier (VLTdSCR) type electrostatic discharge (ESD) protection structure and its cross-coupling ultra-low-triggering ESD protection circuitry (CULTdSCR) implemented in a commercial 0.18 μm CMOS. Mixed-mode ESD simulation-design technique is used to verify the new embedded punch-through and gate cross-coupling ESD trigger-assisting techniques devised to achieve ultra-low ESD triggering for SCR-type ESD protection in CMOS. Experiment shows a record low ESD triggering voltage (Vt1) of 3.83 V, noise figure (NF) of 0.2 dB, parasitic ESD capacitance (CESD) of 150 fF and prompt response to very fast ESD pulses with rising time (tr) down to 100 pS. The new ESD design achieves a very high dual-directional charged device model (CDM) ESD protection capability of ~7 V/μ m2.

This paper presents both an integrated energy supply and detection circuits for an RFID localization system. The equations to calculate the expected AC antenna voltage are presented as well as a fast method to calculate the expected output voltage from a rectifier. An ultra low power voltage detection circuit is described which monitors the output voltage of the rectifier and consumes only 3 nW. Also the input of the rectifier is monitored by an input power dip detection circuit, which provides a pulse whenever the amplitude of the AC antenna signal drops to zero. This circuit too, is ultra low power and consumes only 5 nW from a 0.5 V supply. It can even serve as an OOK demodulator for bitrates up to 6.7 kbps. All circuits have been designed in a 130 nm CMOS process. Measurement results are presented for all circuits.

Energy harvesting is an emerging technology with applications to handheld, portable and implantable electronics. Harvesting ambient vibration energy through piezoelectric (PE) means is a popular energy harvesting technique that can potentially supply 10 to 100's of µW of available power [1]. One of the limitations of existing PE harvesters is in their interface circuitry. Commonly used full-bridge rectifiers and voltage doublers [2] severely limit the electrical power extractable from a PE harvesting element. Further, the power consumed in the control circuits of these harvesters reduces the amount of usable electrical power. In this paper, a bias-flip rectifier that can improve upon the power extraction capability of existing full-bridge rectifiers by up to 4.2× is presented. An efficient control circuit with embedded DC-DC converters that can share their filter inductor with the bias-flip rectifier thereby reducing the volume and component count of the overall solution is demonstrated.

This paper presents an efficiency-enhanced integrated full-wave CMOS rectifier for the transcutaneous power transmission in high-current biomedical implants. The comparator-controlled switches are developed to minimize the voltage drop along the conducting path while achieving the unidirectional current flow. The proposed unbalanced-biasing scheme also minimizes the reverse leakage current of the rectifier under different input amplitudes, thereby optimizing the rectifier power efficiency. Moreover, the proposed rectifier is able to self start and operates at low input amplitudes. Implemented in a standard 0.35 mum CMOS process with maximum threshold voltages of |Vthp| = 0.82 V and Vthn = 0.69 V, the rectifier can source a maximum output current of 20 mA and operate properly with inputs of different amplitudes and frequencies. With a 1.5 MHz input of 1.2 V amplitude, the proposed rectifier can achieve the peak voltage conversion ratio of 95% and the power efficiency of at least 82%.

Piezoelectric transducers are a viable way of harvesting vibrational energy for low power embedded systems such as wireless sensors. A proposed disk-shaped piezoelectric transducer with several electrodes enables increased energy harvesting from multiple mechanical resonances. To rectify the low-frequency AC voltage from harvested vibrational energy, a full-wave rectifier has been fabricated in 0.35 mum CMOS. Integrated peak selection circuitry allows input signals with 90deg relative phase shift from the multiple-electrode piezoelectric transducer to be rectified with reduced output ripple. The rectifier has a measured power efficiency of 98.3% while delivering 90 muW and occupying an area of 0.007 mm2 . This high efficiency further enables energy harvesters to power wireless devices for extended durations.

An RF-DC power conversion system is designed to efficiently convert far-field RF energy to DC voltages at very low received power and voltages. Passive rectifier circuits are designed in a 0.25 mum CMOS technology using floating gate transistors as rectifying diodes. The 36-stage rectifier can rectify input voltages as low as 50 mV with a voltage gain of 6.4 and operates with received power as low as 5.5 muW(22.6 dBm). Optimized for far field, the circuit operates at a distance of 44 m from a 4 W EIRP source. The high voltage range achieved at low load current make it ideal for use in passively powered sensor networks.

This paper proposes temperature-independent load sensor (LS), optimum width controller (OWC), optimum dead-time controller (ODC), and tri-mode operation to achieve high efficiency over an ultra-wide-load range. Higher power efficiency and wider loading current range require rethinking the control method for DC-DC converters. Therefore, a highly efficient tri-mode DC-DC converter is invented in this paper for system-on-chip (SoC) applications, which is switched to sleeping mode at very light load condition or to high-speed mode at heavy load condition. The efficiency improvement is upgraded by inserting new proposed dithering skip modulation (DSM) between conventional pulse-width modulation (PWM) and pulse-frequency modulation (PFM). In other words, an efficiency-improving DSM operation raises the efficiency drop because of transition from PWM to PFM. Importantly, DSM mode can dynamically skip the number of gate driving pulses, which is inverse proportional to load current. Simplistically and qualitatively stated, the novel load sensor automatically selects optimum modulation method and power MOSFET width to achieve high efficiency over a wide load range. Moreover, optimum power MOSFET turn-on and turn-off delays in synchronous rectifiers and reduced ground bounce can save much switching loss by current-mode dead-time controller. Experimental results show the tri-mode operation can have high efficiency about 90% over a wide load current range from 3 to 500 mA. Owing to the effective mitigation of the switching loss contributed by optimum power MOSFET width and reduction of conduction loss contributed by optimum dead-times, the novel width and dead-time controllers achieve high efficiency about 95% at heavy load condition and maintain the highly efficient performance to very light load current about 0.1 mA.

New power conversion circuits to interface to a piezoelectric micro-power generator have been fabricated and tested. Circuit designs and measurement results are presented for a half-wave synchronous rectifier with voltage doubler, a full-wave synchronous rectifier and a passive full-wave rectifier circuit connected to the piezoelectric micro-power generator. The measured power efficiency of the synchronous rectifier and voltage doubler circuit fabricated in a 0.35-/spl mu/m CMOS process is 88% and the output power exceeds 2.5 /spl mu/W with a 100-k/spl Omega/, 100-nF load. The two full-wave rectifiers (passive and synchronous) were fabricated in a 0.25-/spl mu/m CMOS process. The measured peak power efficiency for the passive full-wave rectifier circuit is 66% with a 220-k/spl Omega/ load and supplies a peak output power of 16 /spl mu/W with a 68-k/spl Omega/ load. Although the active full-wave synchronous rectifier requires quiescent current for operation, it has a higher peak efficiency of 86% with an 82-k/spl Omega/ load, and also exhibits a higher peak power of 22 /spl mu/W with a 68-k/spl Omega/ load which is 37% higher than the passive full-wave rectifier.

This paper presents a 950-MHz wireless power transmission system and a high-sensitivity rectifier circuit for ubiquitous sensor network tags. The wireless power transmission offers a battery-life-free sensor tag by recharging the output power of a base station into a secondary battery implemented with the tag. For realizing the system, a high-sensitivity rectifier with dynamic gate-drain biasing has been developed in a 0.3-/spl mu/m CMOS process. The measurement results show that the proposed rectifier can recharge a 1.2-V secondary battery over -14-dBm input RF power at a power conversion efficiency of 1.2%. In the proposed wireless system, this sensitivity corresponds to 10-m distance communication at 4-W output power from a base station.

This paper presents a new electrostatic discharge (ESD) protection design for input/output (I/O) cells with embedded silicon-controlled rectifier (SCR) structure as power-rail ESD clamp device in a 130-nm CMOS process. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. Experimental results have verified that the human-body-model (HBM) ESD level of this new proposed I/O cells can be greater than 5 kV in a 130-nm fully salicided CMOS process. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of the I/O cell.

This paper describes the design and implementation of fully integrated rectifiers in BiCMOS and standard CMOS technologies for rectifying an externally generated RF carrier signal in inductively powered wireless devices, such as biomedical implants, radio-frequency identification (RFID) tags, and smartcards to generate an on-chip dc supply. Various full-wave rectifier topologies and low-power circuit design techniques are employed to decrease substrate leakage current and parasitic components, reduce the possibility of latch-up, and improve power transmission efficiency and high-frequency performance of the rectifier block. These circuits are used in wireless neural stimulating microsystems, fabricated in two processes: the University of Michigan's 3-/spl mu/m 1M/2P N-epi BiCMOS, and the AMI 1.5-/spl mu/m 2M/2P N-well standard CMOS. The rectifier areas are 0.12-0.48 mm/sup 2/ in the above processes and they are capable of delivering >25mW from a receiver coil to the implant circuitry. The performance of these integrated rectifiers has been tested and compared, using carrier signals in 0.1-10-MHz range.

The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.

A pseudologarithmic rectifier using multi-input floating-gate MOS (MFMOS) transistors is presented in this paper. The rectifiers consist of unbalanced bias matched MFMOS transistor differential pairs. The transfer characteristics of each subrectifier are determined by an appropriate choice of transistor aspect ratio and capacitive input coupling ratio such that in the summation of the output currents from each rectifier stage, the overall transfer characteristics closely approximates that of a true logarithmic behavior. It is operable at low supply voltage (/spl plusmn/0.9 V) and has low temperature dependence. Measured dynamic range of 27 dB and 16.5 dB, with a corresponding logarithmic error of /spl plusmn/0.7 dB and /spl plusmn/0.35 dB, has been obtained for three-stage and two-stage pseudologarithmic rectifiers, respectively, at room temperature. The measured logarithmic error for the three-stage pseudologarithmic rectifier at 125/spl deg/C is /spl plusmn/1.05 dB which is an increase of /spl plusmn/0.35 dB over a 100/spl deg/C range.

Modified designs of the low-voltage triggering semiconductor-controlled rectifier (LVTSCR) devices with high trigger current are proposed to protect the CMOS output buffer against electrostatic discharge (ESD) events in submicrometer CMOS technologies. The high trigger current is achieved by inserting the bypass diodes into the structures of the modified PMOS-trigger lateral SCR (PTLSCR) and NMOS-trigger lateral SCR (NTLSCR) devices, these modified PTLSCR and NTLSCR devices have a lower trigger voltage to effectively protect the output transistors in the ESD-stress conditions, but they also have a higher trigger current to avoid the accidental triggering due to the electrical noise on the output pad in the normal operating conditions of CMOS IC's. Experimental results have verified that the trigger current of the modified PTLSCR (NTLSCR) is increased up to 225.5 mA (218.5 mA). The noise margin to the overshooting (undershooting) voltage pulse on the output pad, without accidentally triggering on the modified NTLSCR (PTLSCR), is more than VDD+12 V (VSS-12 V).

A CMOS logarithmic intermediate-frequency (IF) amplifier that is applied to mobile telecommunications equipment is presented. The CMOS logarithmic IF amplifier has pseudologarithmic rectifiers made from parallel-connecting full-wave rectifiers, consisting of unbalanced source-coupled pairs with the cross-coupled input stage and parallel-connected output stage. A +or-3-dB logarithmic accuracy, a 90-dB input dynamic range, and a -30 to 80 degrees C operating temperature range were achieved with the 1.3- mu m double-polysilicon n-well CMOS process. Typical power consumption by the logarithmic IF amplifier in the fabricated CMOS LSI was 5.5 mW. The block area for the logarithmic IF amplifier was 0.8 mm/sup 2/. >

Two bipolar RMS-DC convertor circuits of the computing type which require no rectifier function are discussed. Improved frequency response is thus obtained. RMS-to-DC computation is carried out in the current domain. To make the circuit suitable for voltage driving, a dedicated V-to-I convertor is developed. Measured 1% bandwidths of the RMS-to-DC convertors are 35 and 22 MHz, respectively. Conversion error is less than 1% for the crest factors up to five. >

Describes a bipolar IC analog dynamic range compandor. The approach taken to implement the compressor and expandor functions is discussed, and the active full wave rectifier and variable gain cell are described in detail. Performance easily exceeds telecommunications requirements and is suitable for use in high quality audio systems. The full wave rectifier has excellent accuracy over a 60-dB dynamic range. The variable gain element offers low distortion (