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To design noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs) with high resolution and good power efficiency, two key bottlenecks need to be addressed. One is to realize a high-order loop filter with low circuit overhead, and the other is to mitigate the thermal noise. This article presents an NS-SAR ADC that synergistically addresses both challenges. To achieve high-order efficiency, it proposes an innovative error feedback-cascaded integrator feedforward (EF-CIFF) structure that realizes third-order noise shaping using only a single amplifier. It combines the merits of both structures, showing improved robustness, and is free of dc offset concern. On reducing the kT/C noise, this work features a sampling kT/C noise cancellation (SNC) technique that reuses the native hardware of the EF-CIFF structure. An open-loop self-quenching floating-inverter dynamic amplifier (FIDA) is used to support all amplification with low noise and power. Prototyped in 65-nm CMOS, this work achieves 84.8-dB signal-to-noise-distortion ratio (SNDR) with 625-kHz bandwidth (BW) (OSR = 8) and 119 $\mu \text{W}$ , leading to 182-dB Schreier Figure of Merit (FoM). It uses only 0.8-pF input capacitance, which is $5\times $ smaller than prior NS-SAR ADCs with similar oversampling ratio (OSR) and SNDR.

A pipelined noise-shaping successive approximation register (NS-SAR) ADC with 1–2 multistage noise-shaping (MASH) structure is presented. Two-stage pipelined structure consisting of 5 bit NS-SAR and 4 bit NS-SAR quantizers enables 3rd-order noise-shaping. A single operational transconductance amplifier (OTA) is shared by an integrator for noise-shaping and a residue amplifier for pipelining to maximize the power efficiency. The measured dynamic range (DR) is 84.6 dB when the sampling rate is 83.3 MS/s, bandwidth is 4 MHz, and power consumption is 3.5 mW showing Schreier figure-of-merit (FoMS,DR) of 175.2 dB. The proposed ADC structure greatly relaxes design requirement of each SAR quantizer and can achieve high resolution and wide bandwidth with good power efficiency.

This article presents multi-touch readout IC embedding finger-resistance extraction (FRE) on a capacitive touch screen panel (TSP). The proposed FRE mode is aimed to have the ability to tell users apart while sensing touch input by utilizing a unique finger’s resistance due to different bio-electrical properties. The resonance-driven FRE technique and a clamped zoom-in integrator are exploited to obtain a wide dynamic range (DR). A switched-capacitor current-controlled oscillator-based 14-bit analog-to-digital converter (ADC) was also designed, which has the benefits of low noise, compact size, and high flexibility of its resolution. The prototype chip fabricated in 0.18- $\mu \text{m}$ CMOS achieved the measured signal-to-noise ratio (SNR) of 37.5 dB and DR of 50.7 dB in touch sensing and FRE modes, respectively, in a real-6.7-in capacitive TSP. By applying support vector machine learning to the FRE data, five different user-fingers were successfully classified with 97.7% accuracy after 500 learning cycles and thus demonstrating the feasibility of reliable user-differentiation on multi-user collaborative touch interfaces.

This article presents a low-power audio continuous-time delta-sigma modulator (CTDSM) that employs a chopped negative-R and a tri-level finite impulse-response (FIR) DAC. The noise of the first opamp is mitigated by using a negative-R at the virtual ground of the first integrator, and the negative-R is then chopped to remove the intrinsic ${1/f}$ noise of the negative-R. The highly linear feedback DAC is realized with a 6-tap tri-level FIR-DAC whose inter-symbol interference (ISI) is kept less than −120 dB. The CTDSM fabricated in 65-nm CMOS technology occupies an active area of 0.28 mm2. It achieves 99.4-dB SNDR, 101-dB SNR, 102.8-dB dynamic range (DR), and 110.2-dB SFDR in a 24-kHz bandwidth, while consuming only $134~\mu \text{W}$ . This corresponds to a state-of-the-art figure-of-merit (FoM) of 185.3 dB.

This work introduces a second-order voltage-controlled oscillator (VCO)-based continuous-time delta–sigma modulator (CTDSM) that incorporates a distributed-input VCO as the second-stage integrator and quantizer. The distributed-input VCO topology virtually eliminates the VCO’s voltage-to-frequency (V-F) parasitic pole. One of the key ideas of this article is to demonstrate the use of a capacitive- $\pi $ network in the modulator’s loop filter to break the constraint between the size of the modulator’s inner capacitive digital-to-analog converter (DAC) and the factor by which the front-end Gm-C integrator is impedance scaled. This, in turn, helps to significantly reduce both analog and digital powers. The prototype chip has been fabricated in a 40-nm CMOS process. Despite not using any DAC calibration or explicit dynamic element matching (DEM) circuits, the worst case spurious-free dynamic range (SFDR) is −82 dBc across the signal bandwidth. The fabricated CTDSM achieves a 71.8-dB signal-to-noise-and-distortion ratio (SNDR) and a 74.5-dB dynamic range (DR) in a 10-MHz bandwidth at 655 MS/s, yielding an SNDR-based Walden figure of merit (FoM) of 45.6 fJ/step, an SNDR-based Schreier FoM of 167.2 dB, and a DR-based Schreier FoM of 169.9 dB.

This article presents a Gm-C-based continuous-time delta–sigma modulator (CTDSM) for artifact-tolerant neural recording interfaces. We propose the feedback-assisted Gm linearization technique, which is applied to the first Gm-C integrator by using a resistive feedback digital-to-analog converter (DAC) in parallel to the degeneration resistor of the input Gm. This enables the input Gm to process the quantization noise, thereby improving the input range and linearity of the Gm-C-based CTDSM, significantly. An energy-efficient second-order loop filter is realized by using a voltage-controlled oscillator (VCO) as the second integrator and a phase quantizer. A proportional–integral (PI) transfer function is employed at the first integrator, which minimizes the output swing while maintaining loop stability. Fabricated in a 110-nm CMOS process, the prototype CTDSM achieves a high input impedance, 300-mVpp linear input range, 80.4-dB signal-to-noise and distortion ratio (SNDR), 81-dB dynamic range (DR), and 76-dB common-mode rejection ratio (CMRR) and consumes only 6.5 $\mu \text{W}$ with a signal bandwidth of 10 kHz. This corresponds to a figure of merit (FoM) of 172.3 dB, which is the state of the art among the neural recording ADCs. This work is also validated through the in vivo experiment.

This article presents an incremental two-step capacitance-to-digital converter (CDC) with a time-domain $\Delta \Sigma $ modulator (TD $\Delta \Sigma \text{M}$ ). Unlike the classic two-step CDCs, this work replaces the operational transconductance amplifier (OTA)-based active- RC integrator by a voltage-controlled oscillator (VCO)-based integrator, which is mostly digital and low-power. Featuring the infinite dc gain and intrinsic quantization in phase domain, this TD $\Delta \Sigma \text{M}$ enables a CDC design achieving 76-dB SNDR while requiring only a first-order loop, and a low oversampling ratio (OSR) of 15. Fabricated in 40-nm CMOS technology, the prototype CDC achieves a resolution of 0.29 fF while dissipating only 0.083 nJ/conversion, which improves the energy efficiency by over two times comparing to the similar performance designs.

This article reports a high-linearity dynamic amplifier with a gain control technique for pipelined analog-to-digital converters (ADCs). The wide input range and dynamic operation of the amplifier allow the ADC energy-efficient pipeline process. The voltage gain is controlled in the analog domain with digital gain correction codes, enabling simple compensation for process, voltage, and temperature variations. The proposed switching technique for the amplifier also defines a stable common-mode output without any dedicated hardware. An 11-bit 100-MS/s fully dynamic pipelined ADC using the open-loop dynamic amplifier is implemented without gain-linearity calibration. An ADC prototype is fabricated in a 28-nm CMOS process with an active area of 0.05 mm2, and the performances are measured at sampling rates in the range of 10–100 MHz. This ADC achieves a signal-to-noise and distortion ratio of 62 dB and a spurious-free dynamic range of 77 dB while consuming 1.33 mW of power at 100 MS/s. A Walden figure of merit of 10.8–13.1 fJ/conversion-step is achieved.

Voltage-controlled oscillator (VCO)-based continuous-time $\Delta \Sigma $ modulators (CTDSMs) are deemed attractive for deep-scaled process. However, to realize high-order noise shaping, existing works still employ operational transconductance amplifiers (OTAs), which limits the benefits brought by the VCO. This article presents an OTA-less second-order VCO-based CTDSM featuring a hybrid passive-VCO architecture. It exploits the gain-efficient and scaling-friendly nature of the VCO integrator, enabling the use of a fully passive loop filter to increase the order with minimum power. The proposed architecture is realized in a low-cost, low-noise cascaded-integrator feedback structure that makes use of the parasitic effect of the VCO as an inherent passive stage. Fabricated in 40-nm CMOS, the prototype occupies 0.028 mm2 of active area and consumes 590 $\mu \text{W}$ when sampling at 330 MHz. The CTDSM achieved peak Walden figure of merits of 22 fJ/step with 68.7-dB signal to noise and distortion ratio (SNDR) over 6-MHz bandwidth.

This article demonstrates an analog-to-digital converter (ADC)-based receiver for NRZ/PAM4 modulation, featuring a time-to-digital converter (TDC)-assisted multi-bit/cycle asynchronous successive approximation register (SAR) ADC with embedded IIR equalization filter driven by the differential source followers with an active gain. It re-uses the existing sampling network of time-interleaved (TI) ADCs and incorporates active Gm-C integrators to form a tunable IIR equalizer response. The prototype is fabricated in 65-nm complementary metal–oxide–semiconductor (CMOS) and achieves an efficiency of 2.43-pJ/b using the 12.8-Gbuad PAM4 modulation scheme. The eight-way TI ADC measures 4.84 peak effective number of bit with power consumption of 36.3 mW while occupying 0.24 mm2 core area.

In this article, an efficient technique is introduced to extract the quantization noise of a multi-phase voltage-controlled oscillator (VCO)-based quantizer (VCOQ) in the time domain as a pulsewidth modulated (PWM) signal. Using this technique, a new highly linear VCO-based 1-1 multi-stage noise shaping (MASH) delta–sigma analog-to-digital converter (ADC) structure is presented. This architecture does not require any operational transconductance amplifier (OTA)-based analog integrators or power-hungry linearization methods. The first stage is a closed-loop multi-phase VCO-based voltage-to-phase (V-to-P) converter, and the second stage is an open-loop multi-phase VCO-based voltage-to-frequency (V-to-F) converter. Using the proposed technique, the phase quantization error of the first stage is extracted as a pulse signal and then fed to the second stage. The input of the first VCO is a very small amplitude signal, and the input of the second VCO is a two-level PWM signal. Therefore, the VCO non-linearity does not limit the overall ADC performance, mitigating the need for power-hungry linearization methods. The prototype achieves second-order noise shaping with a DR/SFDR/SNR/SNDR of 82.7/88.7/80.3/79.7 dB for an input signal BW of 2 MHz. The fabricated design consumes 1.248 mW from a 0.9-V supply.

This article presents a discrete-time second-order $\Delta \Sigma $ modulator for the audio applications. In this modulator, a novel dynamic amplifier is proposed to realize the switched-capacitor (SC) integrators. To eliminate the common-mode (CM) voltage drop in a closed-loop dynamic amplifier during the integration phase, without the use of additional load capacitance, the reset method for the amplifier is modified. Two auxiliary branches are introduced to enhance the settling speed of the integrator. Two different flicker noise reduction techniques (FNRTs) are developed to improve the signal-to-noise-and-distortion ratio (SNDR) (about 2 dB in the audio bandwidth). The prototype modulator is fabricated in 65-nm CMOS technology with a 0.12-mm2 core area, which achieves a dynamic range (DR) of 91 dB and a peak SNDR of 89.6 dB in the 24-kHz signal bandwidth. It consumes only 49- $\mu \text{W}$ power from a 0.8-V supply, translating into a Schreier figure of merit (FoM) of 176.5 dB.

The use of continuous-time delta-sigma modulators (CTDSM) as a replacement of traditional analog sensor front ends has become an increasingly popular choice. The absence of traditional sensor interface circuits, such as instrumentation amplifiers (IAs), reduces area and power consumption at the cost of robustness offered by these circuits. Selection of the integrator type in the CTDSM is a selection of the ADC properties. This article presents a current feedback CTDSM with high input impedance, wide linear operating range, and large-signal common-mode rejection as a neural recorder front end. We propose the modification of an IA for operation as an integrator in a delta-sigma modulator and the current reuse of the feedback DAC current to bias this integrator stage. Deploying the current reuse technique, the total power consumption of the modulator is reduced by 22%. The ASIC is developed in a 180-nm high-voltage CMOS technology and the analog front end achieves a dynamic range of 90 dB and a total harmonic distortion (THD) of 0.005% when configured for a full-scale input signal of 208 mVpp. A common-mode rejection ratio (CMRR) of 90 dB is measured for a common-mode disturbance of 325 mVpp while the analog power consumption per channel is 23 $\mu \text{W}$ .

A 2-1 multistage noise-shaping (MASH) switched-capacitor (SC) delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. We developed two separate segmented integration techniques to implement the first two integrators in the DSM. The techniques use both an inverter (IVT)-based opamp and a source-coupled-pair (SCP)-based opamp to relay the charge integration operation. This increases performance while saving power. The first integrator also operates more slowly during output sampling to further reduce power consumption. Operating at a 5-MS/s sampling rate, this chip consumes 175 $\mu \text{W}$ from a 1-V supply. For a 25-kHz signal bandwidth, it achieves a 96.1-dB signal-to-noise ratio (SNR), a 94.6-dB signal-to-noise-plus-distortion ratio (SNDR) and a 98.5-dB dynamic range (DR). Its active area is $1.13\times 0.34\,\,\text {mm}^{2}$ .

This paper presents a 13-bit high-resolution two-step analog-to-digital converter (ADC). Successive approximation register (SAR)-ADCs and an incremental sigma-delta modulator (ISDM) act as the coarse and fine ADCs, respectively. By using the proposed time-domain ISDM, the integrator is relaxed from the finite gain error and static current consumption. For the matching of the capacitive digital-to-analog converter(CDAC), the integral non-linearity (INL) splitting (INLS) switching procedure is developed to reduce the INL and switching energy to 25% and 9% of the reference common-mode voltage (VCM)-based scheme, respectively. With a reduced capacitance of the capacitor array, the requirements of the input driver and reference buffer are effectively relaxed. A prototype was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm CMOS technology, which occupies an area of 0.059 mm2. The achieved spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) at Nyquist rate are 90.38 and 73.57 dB, respectively. The maximum differential non-linearity (DNL) and INL are 0.45 and 0.75 LSB, respectively. The prototype consumes 638 nW at 0.4-V supply and 270-kHz sampling rate. The resultant Schreier figure of merit (FoM) is 186.8 dB, and the Walden FoM is 0.61 fJ/conversion step.

This paper presents a low-power and scaling-friendly noise-shaping (NS) SAR ADC. Instead of using operational transconductance amplifiers that are power hungry and scaling unfriendly, the proposed architecture uses passive switches and capacitors to perform residue integration and realizes the path gains via transistor size ratios inside a multi-path dynamic comparator. The overall architecture is simple and robust. Since the noise transfer function is set by component ratios, it is insensitive to process, voltage, and temperature (PVT) variations. Besides the proposed architecture, this paper also presents two new circuit techniques. A tri-level voting scheme is proposed to reduce the comparator noise. It outperforms the majority voting technique by exploiting more information in the comparator output statistics and providing an extra decision level. A dynamic multi-phase clock generator is also proposed to guarantee non-overlapping and support an arbitrary number of phases. A prototype 9-bit NS-SAR ADC is fabricated in a 40-nm CMOS process. It consumes $143~\mu \text{W}$ at 1.1 V while operating at 8.4 MS/s. Taking advantage of the second-order NS, it achieves a peak SNDR of 78.4 dB over a bandwidth of 262 kHz at the oversampling ratio of 16, leading to an SNDR-based Schreier figure of merit (FoM) of 171 dB.

This paper presents a dynamic power reduction technique for incremental $\Delta \Sigma $ (I- $\Delta \Sigma $ ) modulators. The technique makes use of the unequal weighting of the digital reconstruction filter. The underlying idea is that the input signal samples are not equally weighted in the higher order reconstruction filter. Thus, it is possible to increase the non-idealities of the I- $\Delta \Sigma $ modulator during the runtime of a single Nyquist conversion, thereby saving power. This principal idea is verified by an example design, where the input-referred noise of the first integrator is dynamically increased, which allows for improved efficiency. The proposed technique is readily applicable to every state-of-the-art I- $\Delta \Sigma $ modulator. Furthermore, it is shown that this property can also be used to switch a single-bit digital-to-analog converter (DAC) into a multibit DAC during runtime, thereby greatly improving the achievable signal-to-quantization-noise ratio (SQNR) without suffering from the DAC non-linearity. The prototype I- $\Delta \Sigma $ modulator is manufactured in a 180-nm CMOS technology and achieves a dynamic range/SNDR = 91.5/86.6 dB for a sampling rate of 200 kS/s while consuming l.l mW from a 3-V supply, while the dynamic power reduction method accounts for 30% power savings.

This paper presents a sub-baud-rate clock and data recovery (CDR) circuit that can recover clock and data using only differential quarter-rate clocks. A combination of eight samplers and an integrator recover four data bits in each clock cycle. Four of the eight samplers are re-used for phase detection as well as for background calibration to improve the robustness of the CDR to process, voltage, and temperature variations. A continuous-time linear equalizer is used to compensate for inter-symbol interference up to 11 dB. The CDR prototype fabricated in a 65-nm CMOS recovers 15.2-Gb/s data using only differential 3.8-GHz clock and achieves bit error rate (BER) 10-MHz jitter tolerance (JTOL) corner, and 548 fsrms recovered clock jitter. The total power consumption is 29 mW, which translates to an energy efficiency of 1.9 pJ/bit.

The opamp in the integrators of a continuous-time delta-sigma modulator (CTDSM) has stringent noise and linearity requirements, which lead to large power dissipation. In this paper, a negative-R assisted integrator is proposed to mitigate the opamp’s requirements including dc gain, unity gain bandwidth, thermal and 1/ ${f}$ noise, and linearity, thus enabling a drastic power reduction. We present two prototype CTDSMs using the negative-R assisted integrators that employ a single-bit and tri-level feedback digital-to-analog converter (DAC), respectively. The prototype CTDSMs were fabricated in 65-nm CMOS technology. The first CTDSM using a single-bit feedback DAC achieves dynamic range (DR)/signal to noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 93.1/88.5/100.5 dB in a 20-kHz bandwidth while dissipating only 55 $\mu \text{W}$ from a 1.2-V supply. The second CTDSM, with a tri-level feedback DAC, achieves DR/SNDR/SFDR of 98.2/94.1/107 dB in a 24-kHz bandwidth while dissipating only 68 $\mu \text{W}$ from a 1.2-V supply. The figures of merit of the two CTDSMs are 178.7 and 183.6 dB, respectively, which are the best energy efficiency among state-of-the-art works.

The noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) is an emerging hybrid architecture that achieves high resolution and power efficiency simultaneously by combining the merits of the SAR ADC and the $\Delta \Sigma $ ADC. Most prior works adopting the cascaded integrator feed-forward (CIFF) structure demonstrate inefficiency in realizing optimized noise transfer function (NTF). This paper presents a second-order NS-SAR ADC employing the error-feedback (EF) structure to realize complex NTF zeros for noise-shaping enhancement with the minimum modification to a standard SAR. It implements a low-power scaling-friendly EF path by using a passive finite impulse response (FIR) and a comparator-reused dynamic amplifier with process-voltage-temperature (PVT) tracking background calibration. Fabricated in 40-nm CMOS, the prototype chip consumes $84~\mu \text{W}$ when operating at 10 MS/s. The NS-SAR achieves peak Schreier FoM of 178 dB with 79-dB signal to noise and distortion ratio (SNDR) at an oversampling ratio (OSR) of 8.

Integrated recording of neural electrical potentials from the brain poses great challenges due to stringent dynamic range requirements to resolve small-signal amplitudes buried in noise amidst large artifact and stimulation transients, as well as stringent power and volume constraints to enable minimally invasive untethered operation. Here, we present a 16-channel neural recording system-on-chip with greater than 90-dB input dynamic range and less than 1- $\mu \text{V}_{\mathrm {rms}}$ input-referred noise from dc to 500 Hz, at 0.8- $\mu \text{W}$ power consumption, and 0.024-mm2 area per channel in a 65-nm CMOS process. Each recording channel features a hybrid analog–digital second-order oversampling analog-to-digital converter (ADC), with the biopotential signal coupling directly to the second integrator for high conversion gain and dynamic offset subtraction in the digital domain. This bypasses the need for high-pass filtering pre-amplification in neural recording systems, which often leads to signal distortion. The integrated ADC-direct neural recording offers record figure-of-merit with a noise efficiency factor (NEF) of the combined front end and ADC of 1.81, and a corresponding power efficiency factor (PEF) of 2.6. Predictive digital autoranging of the binary quantizer further supports rapid transient recovery while maintaining fully dc-coupled operation. Hence, the neural ADC is capable of recording ${\le}$ 0.01-Hz slow potentials as well as recovering from $\ge$ 200-mVpp transients within ${\le}$ 1 ms that are important prerequisites to effective electrocortical recording for brain activity mapping. In vivo recordings from marmoset primate frontal cortex demonstrate its unique capabilities in resolving ultra-slow local field potentials indicative of subject arousal state.

This paper presents a $G_{m}$ – $C$ -based $\Delta \Sigma $ modulator under 0.4-V supply. A 3rd-order continuous-time $\Delta \Sigma $ modulator is proposed by cascading three $G_{m}$ – $C$ proportional integra- tors (PIs) with a feedforward resistor for the proportional path, which minimizes the output swing of each integrator and ensures that the last two transconductors operate within their linear input range. A nine-tap finite-impulse response (FIR) digital to analog converter (DAC) in front of the first $G_{m}$ – $C$ integrator filters the large out-of-band quantization noise from the feedback signal, generating a quiet input of the first transconductor for better linearity. A feedback bias control technique is proposed to achieve a stable transconductance of the $G_{m}$ cells under low supply voltages. The proposed $\Delta \Sigma $ modulator is fabricated in a 90-nm CMOS and achieves 74.4-dB peak signal-to-noise and distortion ratio (SNDR), 85.2-dB peak spurious free dynamic range (SFDR), and 78.5-dB dynamic range (DR) within a 50-kHz bandwidth, which is the first demonstration of $G_{m}$ – $C$ -based modulators under near-threshold supply voltages. The FoM w is 61.2 fJ/conversion-step, and FoM s is 167 dB, outperforming the reported low-voltage $\Delta \Sigma $ modulator designs.

This paper reports a continuous-time (CT) third-order delta-sigma modulator that features a single amplifier biquad (SAB) and a passive integrator to simplify the circuit to just one power hungry operation amplifier (opamp). Such setup not only relaxes the gain and bandwidth requirement of the opamp design but also enhances the overall modulator stability which enables a power-efficient loop filter implementation. We used an SAR architecture in the quantizer with an advanced feedback technique to alleviate its speed penalty. By incorporating the proposed CT complementary (CTC) opamp and an adaptive latch scheme in the DAC driver, the modulator attains a signal bandwidth of 10 MHz with 79.6-dB signal-to-noise and distortion ratio (SNDR) while only consuming 5.35 mW from 1.2- and 1.8-V power supplies. The prototype has a dynamic range of 84.5 dB and a Schreier FoM of 177.2 dB with an active area of 0.033 mm2.

This paper presents a 2-2 discrete-time (DT) resolution-enhanced sturdy multi-stage noise-shaping (SMASH) delta–sigma modulator. It uses source-follower-based integrators to efficiently increase the operating speed of a DT modulator. A SMASH topology that consists of two second-order low-distortion feed-forward stages provides an enhanced linearity by reducing the sensitivity to the non-ideal gain and distortion of the proposed integrator. The resolution of the proposed SMASH architecture is improved by eliminating the first-stage quantization noise from the output. In order to reduce power and area of the modulator, one 5-bit feedback digital-to-analog converter is shared for both stages, and the number of comparators for a 4-bit quantizer in the second stage is reduced by scaling the signal swing range. The prototype delta–sigma modulator fabricated in a 65-nm CMOS process achieves a 75.8-dB dynamic range and 72.9-dB signal-to-noise-and-distortion ratio (SNDR) in a 20-MHz bandwidth. From a 1.2-V supply voltage operating at a 500-MHz clock frequency, the total power consumption of the prototype modulator is 20.4 mW, corresponding to a Walden and Schreier figure of merits of 141.3 fJ/conversion-step and 165.7 dB, respectively.

A low-jitter and low-reference-spur ring-type voltage-controlled oscillator (VCO)-based switched-loop filter (SLF) phase-locked loop (PLL) is presented. To enhance the capability of suppressing jitter of a VCO, we propose a fast phase-error correction (FPEC) technique that emulates the phase-realignment mechanism of an injection-locked clock multiplier. By the proposed FPEC technique, accumulated jitter of a VCO can be removed intensively in a short interval, thereby suppressing jitter dramatically. Based on a PLL topology having an intrinsic integrator in a VCO, the proposed architecture can also achieve a low reference spur despite a high multiplication factor (i.e., 64). This paper also presents the selective frequency-tuning technique used in the VCO that helps the proposed architecture further suppress the level of reference spur. The proposed PLL was fabricated in a 65-nm CMOS process. The measured rms jitter integrated from 1 kHz to 80 MHz and the reference spur of the output signal with a 3.008-GHz frequency were 357 fs and −71 dBc, respectively. The total active area was 0.047 mm2, and the power consumption was 4.6 mW.

Chopping the operational transconductance amplifier (OTA) of the input integrator in a CT $\Delta \Sigma \text{M}$ is a traditional and effective way of addressing flicker noise in such modulators. Unfortunately, chopping leads to aliasing of shaped quantization noise into the signal band and degrades performance. We analyze the mechanisms of shaped-noise aliasing in OTA- $RC$ integrators that use two-stage feedforward-compensated OTAs, and show that aliasing can be largely mitigated by using an finite impulse response feedback digital-to-analog converter with its zeros placed at multiples of twice the chopping frequency. The theory is borne out by measurement results from a single-bit CT $\Delta \Sigma \text{M}$ , which achieves a peak SNDR of 98.5 dB in a 24-kHz bandwidth while consuming only 280 $\mu \text{W}$ from a 1.8-V supply. Realized in a 180-nm CMOS technology, it achieves a $1/f$ noise corner of about 3 Hz when chopped at $f_{s}/24$ .

This paper presents the architectural concept and implementation of a mostly digital voltage-controlled oscillator-analog-to-digital converter (VCO-ADC) with third-order quantization noise shaping. The system is based on the combination of a VCO and a digital counter. It is shown how this combination can function as a continuous-time integrator to form a high-order continuous-time sigma–delta modulator (CT-SDM). The counter consists only of digital building blocks, and the VCOs are implemented using ring oscillators, which are also digital-friendly. No traditional analog blocks, such as opamps, OTAs, or comparators, are used. As a proof of concept, we have implemented a third-order VCO-based CT-SDM for a 10-MHz bandwidth in the low-power version of a 65-nm CMOS technology. This prototype shows a measured performance of 71/66.2/62.5-dB DR/SNR/SNDR at a 10-MHz bandwidth while consuming 1.8 mW from a 1.0-V analog and 1.9 mW from a 1.2-V digital supply. With digital calibration, the nonlinearity could be pushed below the noise level, leading to an improved peak SNDR of 66 dB.

This paper presents a multi-step incremental analog-to-digital converter (IADC) using multi-slope extended counting. Only one active integrator is used in the three-step conversion cycle. The accuracy of the IADC is extended by having it configured asmulti-slope ADCs in two additional steps. The proposed IADC uses the same circuitry as a first-order IADC (IADC1), but it exhibits better performance than a second-order IADC. For the same accuracy, the conversion cycle is shortened by a large factor (by more than 29 for the implemented device) compared with that of a conventional single-step IADC1. Fabricated in 0.18 $\mu \text{m}$ CMOS process, the prototype ADC occupies 0.5 mm2. With a 642 kHz clock, it achieves an SNDR of 52.2 dB in the first step. The SNDR is boosted to 79.8 dB in the second step and to 96.8 dB in the third step, over a 1 kHz signal band. The power consumption is 35 $\mu \text{W}$ from a 1.5 V power supply. This gives an excellent Schreier figure of merit of 174.6 dB.

A wide-bandwidth (BW) power-efficient continuous-time ΣΔ modulator (CTΣΔM) is presented. The modulator introduces a third-order filter implemented with a lossless integrator and a multiple-feedback single-amplifier biquadratic filter with embedded loop stability compensation. An active summing block is implemented by employing a common-gate current buffer followed by a transimpedance amplifier. This combination relaxes the specification requirements of the operational amplifier by making its required BW independent of the closed-loop gain. The proposed technique achieves optimum BW with reduced power consumption, making it functional for over gigahertz operation. Fabricated in a standard 40-nm CMOS technology, and clocked at 3.2 GHz, the CTΣΔM achieves a signal-to-noise-and-distortion ratio of 65.5 dB over 75-MHz BW while consuming 22.8 mW of power. The obtained Walden's figure of merits is 98 fJ/conv-step.

This paper presents a readout method and circuit for large, capacitive-type touch-screen panels (TSPs). Despite the considerable amount of RC time delay of large-area TSPs, the proposed readout method with a receiver (Rx) input series-capacitor improves the settling speed of signals transferred from the transmitter (Tx) to the Rx, by reducing the RC time delay. Combined with the Rx input series-capacitor, a capacitive-input fully differential filtered charge integrator effectively cancels out the display noise and reduces the self-noise in capacitive-type TSPs. The proposed Rx circuit was implemented using 0.35- $\mu \text{m}$ CMOS. Using a 65-in metal-mesh TSP with 169 Tx and 97 Rx electrodes mounted on a liquid-crystal display for testing, the proposed readout method achieved 65% reduction of signal settling time within an accuracy of $\geq 3\tau $ for the longest signal path of the TSP. Using the RC time delay reduction technique, the Tx driving frequency could be boosted by as much as 400 kHz, and the measured signal-to-noise ratio of 43.5 dB was obtained for finger touch at a 120-Hz scan rate, resulting in a figure-of-merit of 0.26 nJ/node, while the overall power consumption was 76 mW.

This paper proposes a multistage noise-shaping continuous-time sigma-delta modulator (CT $\Sigma \Delta \text{M}$ ) with on-chip RC time constant calibration circuits, multiple feedforward interstage paths, and a fully integrated noise-cancellation filter (NCF). The core modulator architecture is a cascade of two single-loop second-order CT $\Sigma \Delta \text{M}$ stages, each of which consists of an integrator-based active- RC loop filter, current-steering feedback digital-to-analog converters, and a 4-b flash quantizer. On-chip RC time constant calibration circuits and high-gain multistage operational amplifiers are realized to mitigate quantization noise leakage due to process variation. Multiple feedforward interstage paths are introduced to: 1) synthesize a fourth-order noise transfer function with dc zeros; 2) simplify the design of NCF; and 3) reduce signal swings at the second-stage integrator outputs. Fully integrated in 40-nm CMOS, the prototype chip achieves 74.4 dB of signal-to-noise-and-distortion ratio (SNDR), 75.8 dB of signal-to-noise ratio, and 76.8 dB of dynamic range in 50.3 MHz of bandwidth (BW) at 1 GHz of sampling frequency with 43 mW of power consumption (P) from 1.1/1.15/2.5-V power supplies. It does not require external software calibration and possesses minimal out-of-band signal transfer function peaking. The figure-of-merit (FOM), defined as $\text {FOM}=\text {SNDR}+10\times \log _{10}(\text {BW}/\text {P})$ , is 165.1 dB.

Modern multicore processors employ multiple phase-locked loops (PLLs) to operate individual cores at a power-optimal frequency. This paper presents techniques to implement such PLLs in a small area. The area occupied by classical charge-pump-based analog PLLs is mostly due to the large loop filter capacitor needed to implement the integral control portion of type-II response. Digital PLLs (DPLL) can eliminate the capacitor by implementing the integral control in digital domain but their jitter performance is degraded by the quantization error introduced by DPLL building blocks such as a time-to-digital converter (TDC). We seek to combine the advantages of analog (no quantization error) and digital (small area) PLLs by implementing the integral control using time-based techniques. To this end, a ring oscillator-based integrator (ROI) is used to implement the integral control. ROI integrates its input and generates an output in the form of a pulse-width modulated (PWM) signal. While the ROI does not introduce quantization error, controlling the voltage controlled oscillator with the PWM signal introduces undesirable spurious tones. We propose to use a pseudo-differential ROI to mitigate these tones and achieve good jitter performance. Fabricated in 65 nm CMOS LP process, the prototype PLL occupies an active area of only 0.0021 mm2 and operates across a supply voltage range of 0.6 V to 1.2 V providing 0.4–2.6 GHz output frequencies. At 2.2 GHz output frequency, the PLL consumes 1.82 mW at 1 V supply voltage, and achieves 3.73 psrms integrated jitter. This translates to an FoMJ of −226.0 dB, which compares favorably with state-of-the-art designs while occupying the smallest reported active area.

An ultra-thin ( $20\;\bm{\upmu} {\bf m}$ ), flexible CMOS stress sensor for hybrid systems-in-foil (HySiF) is presented. The system is designed for Fin Ray® grippers in order to measure the emerging stress on the gripper in operation, enabling the extraction of object shape and operation status. In-plane stress is linearly converted to electrical signals proportional to shear stress and normal stress difference using two sensing elements. Each stress signal is processed and digitized by an integrator and a 10-bit SAR ADC. In contrast to rigid chips, the stress cannot be avoided in the sensitive blocks, such as the signal processing chain and digital controller, when an ultra-thin chip is under deformation. The influence of stress levels, up to 350 MPa, is minimized by using stress-insensitive components, design measures, and layout techniques. This work represents the first demonstration of stress-aware top-to-bottom CMOS design on an ultra-thin chip.

This article reports a 4th-order 100-MHz bandwidth continuous-time (CT) delta–sigma modulator in 28-nm CMOS. A preliminary sampling and quantization (PSQ) technique is presented, which allows almost a full utilization of the clock period for the quantization to extend the available conversion time of the backend quantizer (QTZ) under a 0.65 excess loop delay (ELD) coefficient. With the PSQ, both the sampling and quantization of the backend QTZ are splitted into two steps, coarse and fine, similar to the subranging architecture to save power. The QTZ runs at 2 GHz achieving 7 bit (1 b error correction) with only 1.4-mW power. By adding a feedforward ELD compensation path in the cascade of integrators of the cascade of integrators in feedforward (CIFF) topology, only one digital-to-analog converter (DAC) is necessary in this design. The modulator attains a signal bandwidth of 100 MHz with 72.6-dB signal-to-noise and distortion ratio (SNDR) while only consuming 16.3 mW from 1.1- and 1.5-V power supplies. The prototype has a dynamic range of 76.3 dB and a Schreier FoM of 174.2 dB with an active area of 0.019 mm2.

This work presents a compact-area hybrid continuous-time delta-sigma modulator (CTDSM) with a shared 6 bit asynchronous successive approximation register (ASAR) quantizer for audio application. It is implemented in a 28 nm CMOS process. The modulator incorporates an analog integrator and a digital filter. Signal is digitized after the analog first stage and processed digitally thereafter. Only the first stage is left in the analog domain. Because of high integration of digital circuitry, it could benefit from process advancement such as low power consumption and small area. Moreover, the excess loop delay (ELD) is compensated in the digital domain, and the conventional analog local feedback DAC for ELD compensation is no longer needed. In addition, resistive DAC (R-DAC) is adopted for low flicker noise. The measured DR and SNDR in 24 kHz BW are 100.6 dB and 98.5 dB, respectively, while occupying 0.022 mm 2 and achieving FOMs (SNDR + 10 $*$ log(BW/Power)) of 171.8 dB.

This paper presents a delta-sigma modulator operating at a supply voltage of 0.4 V. The designed delta-sigma modulator uses a proposed hybrid switching integrator and operates at a low supply voltage without clock boosting or bootstrapped switches. The proposed integrator consists of both switched-resistor and switched-capacitor operations and significantly reduces distortion at a low supply voltage. Variation in the turn-on resistance, which is the main source of distortion, is avoided by placing the switches at the virtual ground node of the amplifier. The proposed low-voltage design scheme can replace commonly-used clock boosting techniques, which rely on internal high-voltage generation circuits. A fabricated modulator achieves a 76.1 dB signal-to-noise-plus-distortion ratio (SNDR) and an 82 dB dynamic range at a 20 kHz bandwidth. The measured total power consumption is 63 µW from a 0.4 V supply voltage. The measured results show robust SNDR performance, even at ±10% supply voltage variations. The measured results also show stable performance over a wide temperature range.

This paper presents a voltage-controlled oscillator (VCO) based current to digital converter for sensor readout applications. Second order noise shaping of the quantization error is achieved by using implicit capacitance of the sensor to realize a passive integrator and a VCO-based quantizer. The non-linearity in voltage to frequency conversion of the VCO is tackled by placing the VCO in a loop consisting of a simple digital IIR filter and a passive integrator. The IIR filter provides large gain within the signal bandwidth and suppresses VCO input swing. As a result, non-linearity of the VCO is not exercised, thus greatly improving the proposed architecture's immunity to VCO nonlinearity. The use of a digital filter instead of an analog loop filter eases the design and makes it scaling friendly. Designed for an ambient light sensor application, the proposed circuit achieves 900 pA accuracy over an input current range of 4 $\mu$ A. Fabricated in a 0.18 $\mu$ m CMOS process, the readout circuit consumes a total of 77.8 $\mu$ A current, and occupies an active area of 0.36 mm $^2$ .

Time-based control techniques for the design of high switching frequency buck converters are presented. Using time as the processing variable, the proposed controller operates with CMOS-level digital-like signals but without adding any quantization error. A ring oscillator is used as an integrator in place of conventional opamp-RC or G $_{\rm m}$ -C integrators while a delay line is used to perform voltage to time conversion and to sum time signals. A simple flip-flop generates pulse-width modulated signal from the time-based output of the controller. Hence time-based control eliminates the need for wide bandwidth error amplifier, pulse-width modulator (PWM) in analog controllers or high resolution analog-to-digital converter (ADC) and digital PWM in digital controllers. As a result, it can be implemented in small area and with minimal power. Fabricated in a 180 nm CMOS process, the prototype buck converter occupies an active area of 0.24 mm $^{2}$ , of which the controller occupies only 0.0375 mm $^{2}$ . It operates over a wide range of switching frequencies (10–25 MHz) and regulates output to any desired voltage in the range of 0.6 V to 1.5 V with 1.8 V input voltage. With a 500 mA step in the load current, the settling time is less than 3.5 $\mu$ s and the measured reference tracking bandwidth is about 1 MHz. Better than 94% peak efficiency is achieved while consuming a quiescent current of only 2 $\mu$ A/MHz.

This paper presents a power-efficient 80 MS/s, 11 bit ENOB ADC. It is realized in 28 nm CMOS and is based on two interleaved pipelined SAR ADCs. It includes an on-chip reference generator and does not require any external components. The total power dissipation is 1.5 mW, resulting in a low-frequency Walden FOM of 9.1 fJ/conv-step and a low-frequency Schreier FOM of 172.2 dB, which is the largest FOM reported to date for sampling frequencies larger than 1 MS/s. The key aspects in achieving this excellent power efficiency include the choice of ADC architecture, integrator-based amplifiers used for noise filtering, the finite settling of the reference voltage during the SAR conversion, and the modified DAC switching scheme to reduce the DAC switching energy.

Single-bit continuous-time delta-sigma modulators (CTDSM) using FIR feedback DACs inherit the appealing aspects of both single-bit and multibit designs, without the disadvantage of either approaches. In this work, we give a method for stabilizing a CTDSM that uses an FIR feedback DAC. Further, we show that increasing the number of taps beyond a certain number (dependent on the architecture and oversampling ratio of the modulator) does not improve performance. The results of our analysis are incorporated in the design of a third-order audio CTDSM which achieves a peak A-weighted SNR of 102.3 dB (raw SNR of 98.9 dB) and a spurious-free dynamic range of 106 dB in a 24 kHz bandwidth, while consuming only 280 ?W from a 1.8 V supply.

We present design techniques for the realization of compact, low-power CT- ΣΔ-ADCs in ultra-deep-submicron CMOS: A resonant single-opamp third-order integrator with loss compensation, an inverter-based opamp with digitally assisted biasing and common mode control, a pseudo-differential modulator topology with quasi-1.5-bit quantization, a jitter-noise-reduction DAC with NRZ pulse shape, a mismatch-tolerant IIR quantizer, linearized single-ended FIR-DACs with passive DT compensation, and a rail-to-rail dynamic latched comparator. A highly compact 41.4 fJ/conv.-step, 77 dB-SFDR, 1.1 V ADC has been implemented to prove these concepts. The entire active analog circuitry in this minimalistic third-order modulator consists of only ten CMOS inverters.

A 1-0 MASH ΣΔ analog-to-digital converter (ADC) demonstrates a digital linearization technique for the first time treating integrator distortion with memory and capacitor mismatch errors. A two-tap sequential polynomial derived from an output-referred error analysis accurately models the non-ideality of a first-order modulator. The model parameters are extracted by correlating various moments of the ADC digital output with a one-bit pseudorandom noise (PN) superimposed on the input, largely reducing the circuit overhead associated with the nonlinear calibration. The prototype ADC employing amplifiers with a gain of roughly 30 dB measures an 85-dBc spurious-free dynamic range (SFDR) and a 67-dB signal-to-noise and distortion ratio (SNDR) for a 1.1- VPP ( -1-dBFS), 4.99-MHz sinusoidal input at 240 MHz sampling clock (8× OSR) with a 7.5-msec calibration time. For a 1.1- VPP two-tone input at 14.9 MHz and 15.1 MHz, the third-order intermodulation product (IM3) after calibration is 87.1 dBc, which is over 30 dB better than that without calibration. The core ADC consumes 37 mW from a 1.25-V supply and occupies 0.28 mm 2 in a 65-nm CMOS low-leakage digital process in which the transistor threshold voltages are around 0.5 V.

In a conventional bio-sensor, key signal features are acquired using Nyquist-rate analog-to-digital conversion without exploiting the typical bio-signal characteristic of sparsity in some domain (e.g., time, frequency, etc.). Compressed sensing (CS) is a signal processing paradigm that exploits this sparsity for commensurate power savings by enabling alias-free sub-Nyquist acquisition. In a severely energy constrained sensor, CS also eliminates the need for digital signal processing (DSP). A fully-integrated low-power CS analog front-end (CS-AFE) is described for an electrocardiogram (ECG) sensor. Switched-capacitor circuits are used to achieve high accuracy and low power. Implemented in 0.13 μm CMOS in 2×3 mm2, the prototype comprises a 384-bit Fibonacci-Galois hybrid linear feedback shift register and 64 digitally-selectable CS channels with a 6-bit C-2C MDAC/integrator and a 10-bit C-2C SAR ADC in each. Clocked at 2 kHz, the total power dissipation is 28 nW and 1.8 μW for one and 64 active channels, respectively. CS-AFE enables compressive sampling of bio-signals that are sparse in an arbitrary domain.

A third-order single-loop continuous-time sigma-delta modulator (CTSDM) with 6-bit asynchronous successive approximation register (ASAR) quantizer and digital ΔΣ truncator for WCDMA/GSM/EDGE cellular systems is presented. The proposed ASAR-based quantizer reduces the area and power of the modulator dramatically by utilizing the digital truncation technique. By using the 6-bit ASAR quantizer, the sampling frequency is lowered, which reduces the design efforts not only in system level but also in the modulator. In addition, the ac-coupled push-pull stage is employed to improve the high-frequency driving capability of the first integrator. Sampling at 65 MHz, the modulator achieves 83.4 dB dynamic range (DR) and 80/79.6 dB peak SNR/SNDR with 1.92 MHz bandwidth in WCDMA mode. In GSM/EDGE mode, the DR is 96.2 dB. Fabricated in 40-nm CMOS, the modulator occupies 0.051 mm 2 and consumes 1.91 mW from a 1.2-V supply. A 64fJ/conv.-step figure of merit is achieved.

A fourth-order discrete-time delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. It combines low-complexity circuits and digital calibrations to achieve high speed and high performance. The DSM is a cascade of two second-order loops. It has a sampling rate of 1.1 GHz and an input bandwidth of 16.67 MHz with an oversampling ratio of 33. It uses high-speed opamps with a dc gain of only 10. Two different types of digital calibrations are used. We first employ the integrator leakage calibration to correct the poles of the integrators. We then apply the noise leakage calibration to minimize the leaking quantization noise from the first loop. The noise leakage calibration also relaxes the component-matching requirements. Both calibrations can operate in the background without interrupting the normal DSM operation. The chip's measured signal-to-noise-and-distortion ratio and dynamic range are 74.32 and 81 dB, respectively. The chip consumes 94 mW from a 1 -V supply. The active area is 0.33 × 0.58 mm2.

A class-D amplifier with pulse code modulated (PCM) digital input is developed for a low-power digital hearing aid. A 16-bit 40-kbps PCM digital input is noise-shaped by a third-order digital sigma-delta modulator (SDM) which provides 1.5-bit digital output. The 1.5-bit digital output of the digital SDM is converted to a three-level analog signal by a simple digital-to-analog converter (DAC) and then applied to an analog SDM. The analog SDM provides pulse density modulated (PDM) signal to drive a power switch. The PDM output is fed back to the input of the analog SDM in order to suppress the noise of the power switch. While the integrators of the analog SDM are implemented with switched-capacitor (SC) circuits for a well-defined frequency response of the modulator loop filter, the feedback path from the power switch output is realized with a continuous-time (CT) integrator for effective noise suppression. The class-D amplifier with PCM digital input has been implemented in a standard 0.13-μm CMOS process. With 160-Ω load of speaker, the maximum output power delivered to the load is 1.14-mW while the efficiency of the power switch is 97-%. The signal\mathchar"702D to\mathchar"702D noise+distortionnratio (SNDR) and dynamic range (DR) of the class-D amplifier are measured to be 80.6-dB and 87-dB, respectively. The class-D amplifier consumes 0.38-mW from a 1.2-V power supply including the driving power of the power switch.

Although charge-redistribution successive approximation (SAR) ADCs are highly efficient, comparator noise and other effects limit the most efficient operation to below 10-b ENOB. This work introduces an oversampling, noise-shaping SAR ADC architecture that achieves 10-b ENOB with an 8-b SAR DAC array. A noise-shaping scheme shapes both comparator noise and quantization noise, thereby decoupling comparator noise from ADC performance. The loop filter is comprised of a cascade of a two-tap charge-domain FIR filter and an integrator to achieve good noise shaping even with a low-quality integrator. The prototype ADC is fabricated in 65-nm CMOS and occupies a core area of 0.03 mm2. Operating at 90 MS/s, it consumes 806 μW from a 1.2-V supply.

This paper presents an energy-efficient capacitive-sensor interface with a period-modulated output signal. This interface converts the sensor capacitance to a time interval, which can be easily digitized by a simple digital counter. It is based on a relaxation oscillator consisting of an integrator and a comparator. To enable the use of a current-efficient telescopic OTA in the integrator, negative feedback loops are applied to limit the integrator's output swing. To obtain an accurate ratiometric output signal, auto-calibration is applied. This eliminates errors due to comparator delay, thus enabling the use of a low-power comparator. Based on an analysis of the stability of the negative feedback loops, it is shown how the current consumption of the interface can be traded for its ability to handle parasitic capacitors. A prototype fabricated in 0.35 μm standard CMOS technology can handle parasitic capacitors up to five times larger than the sensor capacitance. Experimental results show that it achieves 15-bit resolution and 12-bit linearity within a measurement time of 7.6 ms for sensor capacitances up to 6.8 pF, while consuming only 64 μA from a 3.3 V power supply. Compared to prior work with similar performance, this represents a significant improvement in energy efficiency.

A power and area efficient sensor interface consumes 6.4 mW from 1.2 V while occupying 5 mm × 5 mm in 0.13 μm CMOS. The interface offers simultaneous access to 96 channels of broadband neural data acquired from cortical microelectrodes as part of a head-mounted wireless recording system, enabling basic neuroscience as well as neuroprosthetics research. Signals are conditioned with a front-end achieving 2.2 μVrms input-referred noise in a 10 kHz bandwidth before conversion at 31.25 kSa/s by 10-bit SAR ADCs with 60.3 dB SNDR and 42 fJ/conv-step. Switched-capacitor filtering provides a well-controlled frequency response and utilizes windowed integrator sampling to mitigate noise aliasing, enhancing noise/power efficiency.

A digital correction scheme that allows a switched-capacitor (SC) ΔΣ ADC to operate with significantly reduced power consumption is proposed. As power dissipation is reduced in the integrators, nonlinear settling errors cause increasing harmonic distortion. The correction technique uses a polynomial approximation to correct the nonlinearity and reduce distortion in the post-filtered digital output. With correction, experimental results yield a peak SNDR of 75 dB, a THD of -90 dB and a SFDR of 94 dB. The total analog power dissipation of the corrected modulator is 5 mW at 2.4 V, saving 38% over a similarly performing uncorrected modulator output. The active area is 0.39 mm2 in 0.25-μ m CMOS.