1. Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors
- Author
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Masami Nakajima, N. Masui, Kazuya Ishida, Masayuki Sato, Takashi Nasu, Hayato Fujiwara, Osamu Yamamoto, Mamoru Sakugawa, Hiroyuki Kondo, T. Itoh, Koichi Ishimi, Takashi Higuchi, Sugako Otani, Satoshi Kaneko, Y. Takata, Naoto Okumura, Kazutami Arimoto, and H. Takata
- Subjects
Multi-core processor ,Computer science ,business.industry ,CPU cache ,Controller (computing) ,Process (computing) ,Parallel computing ,ComputerSystemsOrganization_PROCESSORARCHITECTURES ,Embedded system ,Low-power electronics ,System on a chip ,Electrical and Electronic Engineering ,business ,Cache coherence ,System bus - Abstract
A multicore system-on-chip (SoC) has been developed for various applications (recognition, inference, measurement, control, and security) that require high-performance processing and low power consumption. This SoC integrates three types of synthesizable processors: eight CPUs (M32R), two multi-bank matrix processors (MBMX), and a controller (M32C). These processors operate at 1 GHz, 500 MHz, and 500 MHz, respectively. These three types of processors are interconnected on this chip with a high-bandwidth multi-layer system bus. The eight CPUs are connected to a common pipelined bus using a cache coherence mechanism. Additionally, a 512-kB L2 cache memory is shared by the eight CPUs to reduce internal bus traffic. A multi-bank matrix processor with 2-read/1-write calculation and background I/O operation has been adopted. The 1-GHz CPU is realized using a delay management network which consists of delay monitors that can be applied for any kind of application or process technology. Our configurable heterogeneous architecture with nine CPUs and two matrix processors reduces power consumption by 45%.
- Published
- 2008