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This article presents a wideband millimeter-wave (mmWave) receiver front-end that covers the frequency range from 43 to 97 GHz, supporting the operation in the major parts of the V-, E-, and W-bands. The front-end incorporates a passive mixer-first topology to achieve high linearity and wideband performance. The front-end adopts I/Q generation at the RF port, using a coupled-line coupler (CLC), rather than at the local oscillator (LO) port to mitigate the crosstalk of the overlapping I/Q LO signals especially present at high frequencies. The CLC at the RF input facilitates ultrawide band input matching. The front-end implements the multi-gate gm3 cancellation technique at the IF amplifiers to preserve the linearity and provide gain at the IF section. Image rejection capabilities using a current mode transformer-based IF 90° coupler are implemented on chip and demonstrated with measurements. The front-end prototype is fabricated on the GlobalFoundries 22-nm FD-SOI CMOS process and it demonstrates an ultra-wideband performance across the frequency range 43–97 GHz (2.25:1 bandwidth) with image rejection of up to 32 dB, IIP3 of 1.6–5.2 dBm, and gain of 15 dB. The implementation used is low-IF topology with 3.8-GHz IF frequency and 1-GHz bandwidth. Furthermore, the measurement results show that the front-end supports high-speed modulated signals of up to 6-Gbps 64QAM modulation data. [ABSTRACT FROM AUTHOR]

Closed-loop neuromodulation is essential for the advance of neuroscience and for administering therapy in patients suffering from drug-resistant neurological conditions. Neural stimulation generates large differential and common-mode (CM) artifacts at the recording sites, which easily saturate traditional recording front ends. This paper presents a neural recording chopper amplifier capable of handling in-band 80-mVpp differential artifacts and 650-mVpp CM artifacts while preserving the accompanying small neural signals. New techniques have been proposed that introduce immunity to CM interference, increase the input impedance of the chopper amplifier to 1.6 \textG\Omega , and increase the maximum realizable resistance of duty-cycled resistors (DCR) to 90 \textG\Omega . These techniques enable our recording front-end to achieve a dynamic range of 74 dB (200 Hz–5 kHz) and 81 dB (1–200 Hz). Implemented in a 40-nm CMOS process, the prototype occupies an area of 0.069 mm2/channel, and consumes 2.8 \mu \textW from a 1.2-V supply. The input-referred noise is 5.3 \mu \textV\mathrm {\mathbf {rms}} (200 Hz–5 kHz) and 1.8 \mu \textV\mathrm {\mathbf {rms}} (1–200Hz). The total harmonic distortion for a 40-mV \mathrm {\mathbf {p}} input at 1 kHz is −76 dB. This work improves the input impedance by 5.3 $\times $ for chopped front-ends, linear-input range by 2 $\times $ , maximum resistance of DCR by 32 $\times $ , and tolerance to CM interferers by 6.5 $\times $ , while maintaining comparable power and noise performance. [ABSTRACT FROM AUTHOR]

Closed-loop neuromodulation is an essential function in future neural implants for delivering efficient and effective therapy. However, a closed-loop system requires the neural-recording front-end to handle large stimulation artifacts—a feature not supported by most state-of-the-art designs. In this paper, we present a neural-recording front-end that has an input range of ±50 mV and can be used in closed-loop systems. The proposed front-end avoids the saturation due to stimulation artifacts by employing a voltage-controlled oscillator (VCO) to directly convert the input signal into the frequency domain. The VCO nonlinearity is corrected using area-efficient foreground polynomial correction. Implemented in a 40-nm CMOS process, the design occupies 0.135 mm ^\mathrm 2 with an analog power of 3 \mu \textW and a digital switching power of 4 \mu \textW . It achieves ten times higher linear input range than prior art, and 79-dB spurious-free dynamic range at peak input, with an input-referred noise of 5.2 \mu \textV\mathrm { {rms}} across the local-field-potential band of 1–200 Hz. With on-chip subhertz high-pass filters realized by duty-cycled resistors, the front-end also eliminates the need of off-chip dc-blocking capacitors. [ABSTRACT FROM AUTHOR]

This paper presents a 1.6-mW 2.4-GHz receiver that operates from a single supply of 300 mV allowing direct powering from various energy harvesting sources. We extensively utilize transformer coupling between stages to reduce headroom requirements. We forward-bias bulk-source junctions to lower threshold voltages where appropriate. A single-ended 2.4 GHz RF input is amplified and converted to a differential signal before down-converting to a low IF of 1 to 10 MHz. A chain of IF amplifiers and narrowband filters are interleaved to perform programmable channel selection. The chip is fabricated in a 65-nm CMOS process. The receiver achieves -91.5-dBm sensitivity for a BER of 10e-3. [ABSTRACT FROM PUBLISHER]

This paper presents the design and implementation of a novel multi-antenna receiver front-end, which is capable of accommodating various multi-antenna schemes including spatial multiplexing (SM), spatial diversity (SD), and beamforming (BF). The use of orthogonal code-modulation at the RF stage of multi-antenna signal paths enables linear combination of all mutually orthogonal code-modulated RF received signals. The combined signal is then fed to a single RFlbaseband/ADC chain. In the digital domain, all antenna signals are fully recovered using matched filters. Primary advantages of this architecture include a significant reduction in area and power consumption. Moreover, the path-sharing of multiple RF signals mitigates the issues of LO routing/distribution and cross-talk between receive chains. System-level analyses of variable gain/dynamic range, bandwidth/area/power trade-off, and interferers are presented. Designed for the 5-GHz frequency and fabricated in 0.18 μm CMOS, the 76 mW 2.3 mm[sup2] two-antenna receiver front-end prototype achieves a 10[sup-2] symbol error rate (SER) at 64, 77, and 78 dBm of input power for SM, SD, and BF, respectively, while providing 21-85 dB gain, 6.2 dB NF, and 10.6 dBm IIP3. [ABSTRACT FROM AUTHOR]

This paper describes a novel monolithic low voltage (l-V) CMOS RF front-end architecture with an integrated quadrature coupler (QC) and two subharmonic mixers for direct-down conversion. The LC-folded-cascode technique is adopted to achieve low-voltage operation while the subharmonic mixers in conjunction with the QC are used to eliminate LO self-mixing. In addition, the inherent bandpass characteristic of the LC tanks helps suppression of LO leakage at RF port. The circuit was fabricated in a standard 0.18-μm CMOS process for 5-6 GHz applications. At 5.4 GHz, the RF front-end exhibits a voltage gain of 26.2 dB and a noise figure of 5.2 dB while dissipating 45.5 mW from a 1.0-V supply. The achieved input-referred DC-offset due to LO self-mixing is below —110.7 dBm. [ABSTRACT FROM AUTHOR]

This paper addresses the problem of 5-6-GHz WLAN interferer rejection in a direct-conversion receiver front-end for multi-band orthogonal frequency division multiplexing (OFDM) ultra-wideband (UWB) applications. The IC, realized in a 0.18-µm CMOS technology, comprises a single-ended voltage-voltage feed- back low-noise amplifier (LNA) and a quadrature mixer. The LNA employs a double-peak single-notch network in the output load, amplifying UWB groups #1 and #3, while rejecting WLAN interferes in the 5-6-GHz frequency range. The mixer, based on a merged quadrature topology, also realizes a second-order low-pass filtering. Fabricated dies have been bonded on PCB for characterization. The front-end, drawing 10 mA from 1.8 V, achieves a 1-dB gain desensitization with a -6.5-dBm interferer power at 5.5 GHz. Other measured performances are 5.2-dB and 7.7-dB minimum and maximum noise figure (NF), -3.5-dBm minimum IIP3 and +34.5-dBm minimum in-band IIP2 and +21-dBm out-of-band IIP2. [ABSTRACT FROM AUTHOR]

A very-low-cost wireless personal area network (WPAN) receiver implemented in 0.25-µm CMOS technology consumes 17mW of power and occupies an area of 0.66 mm². Simplicity in the physical layer, which still supports the 1-Mb/s requirement, allows for power savings in the receive front-end. A new coding scheme permits the integration of a high-pass filter to mitigate DC offset and 1/f noise. A linear front-end eliminates the external band-preselect filter. This die area is the smallest reported for Bluetooth-class front-ends. [ABSTRACT FROM AUTHOR]

This paper describes a highly digitized direct con- version receiver of a single-chip quadruple-band RF transceiver that meets GSM/GPRS and EDGE requirements. The chip uses an advanced 0.25-µm BiCMOS technology. The I and Q on-chip fifth-order single-bit continuous-time sigma-delta (ΣΔ) ADC has 84-dB dynamic range over a total bandwidth of ±135 kHz for an active area of 0.4 mm². Hence, most of the channel filtering is realized in a CMOS. IC where digital processing is achieved at a lower cost. The systematic analysis of dc offset at each stage of the design enables to perform the dc offset cancellation loop in the digital domain as well. The receiver operates at 2.7 V with a current consumption of 75 mA A first-order substrate coupling analysis enables to optimize the floor plan strategy. As a result, the receiver has an area of 1.8 mm². [ABSTRACT FROM AUTHOR]

A dual-band front-end with two gain modes operating at the 2.4 Industrial Scientific and Medical (ISM) band and 5.15-GHz Unlicensed National Information Infrastructure (UNII) band has been demonstrated in a 0.18-µm foundry CMOS process. The front-end uses a single set of RF blocks. A dual-band low noise amplifier (LNA) with two inputs is tuned to the two resonant frequencies by controlling the voltage on a switched resonator. The same switched resonator is also used to switch the LNA between high-gain and low-gain modes. In the 2.4-GHz high-gain mode, the front-end exhibits 39.8-dB maximum voltage gain, 1.5-dB double-side-band (DSB) noise figure, and -12.7-dBm input-referred IP3 (IIP3) while consuming 24 mW from a 1.8-V supply. In the 5.15-GHz high-gain mode, the front-end achieves 29.2-dB maximum voltage gain, 4.1-dB DSB noise figure and -4.1-dBm IIP3 with 41-mW power consumption. The gains can be switched by 7 dB at 5.15 GHz and by 17 dB at 2.4 GHz. [ABSTRACT FROM AUTHOR]

A low-noise amplifier (LNA) and mixer circuit in 0.35-μm CMOS operates at 2.1 GHz. Merging the LNA and mixer lowers the number of transistors in the signal path and thereby also the nonlinearity and power consumption. The circuit meets the specifications for a direct conversion wide-band code-division multiple access (WCDMA) receiver. Its noise figure is 3.4 dB (5kHz to 5MHz), the total conversion gain is 23 dB, the third-order input-referred intercept point is -1.5 dBm, and the local oscillator leakage to the antenna is less than -71 dBm. The fully differential circuit takes 8 mA from a 2.7-V supply. [ABSTRACT FROM PUBLISHER]