Search

This article presents a single-channel 3.3-GS/s 6-b pipelined analog-to-digital converter (ADC), which features a post-amplification residue generation (PARG) scheme, linearized dynamic amplifier (DA), and on-chip calibration to achieve a high speed, low power, and compact prototype. The PARG scheme allows the quantization and amplification to run in parallel for a fast pipelining operation. The 6-b ADC consists of six pipelined stages with six comparators and five amplifiers in total. Such a small number of hardware reduce the overhead from the calibration and enable fully on-chip implementation. By further sharing the calibration hardware between the offset and gain calibration, the ADC with on-chip calibration only occupies 0.0166 mm² in 28-nm CMOS. With a linearized DA for the residue amplification, the ADC achieves 34-dB signal-to-noise and distortion ratio (SNDR) with a Nyquist input with 3.3 GS/s, consuming 5.5 mW and yielding a 40.02-fJ/conversion-step Walden figure of merit (FoM).

This study presents a design of a 94-GHz high-performance and highly compact frequency-modulated continuous-wave radar sensor. In this sensor, an X-band CMOS-based all-digital phase-locked loop chip, W-band SiGe-based transceiver monolithic microwave integrated circuit (MMIC), and W-band GaN-based MMIC power amplifier (PA) are heterogeneously integrated (HI). Each part of the 130-nm bipolar complementary metal-oxide-semiconductor (BiCMOS) SiGe-based transceiver MMIC is designed to include a low-noise amplifier, PA, octupler, mixer, and lange coupler. The fabrication process of our in-house silicon-based MEMS photosensitive composite film is developed to provide very high-density integration and very low insertion loss of interconnections between chips. The HI front end of the radar sensor is measured on-wafer with a high output power of 22 dBm. Moreover, a low double-sideband noise figure (NF) of 10.2 dB is obtained. Bonding-substrate integrated waveguide (SIW)-WG transitions between the heterogeneously integrated front end and the antenna are specially designed and verified. A 2.3-dB degradation is observed, where 19.7 dBm is measured at the transmitter WG WR-10-flange. Thus, the sensor offers a 55-dB dynamic range at a 2-m position with an expectation of a long-distance target-detection range. The radar sensor has an 11.7-cm range resolution and is only 60 x 40 x 8 mm³ in size, with a weight of only 78 g.

This article presents a 15-bit quadrature digital power amplifier (DPA) with in-phase and quadrature (IQ)-cell-sharing and transformer-based Doherty operation, which compensates the 3-dB power loss in traditional quadrature architecture and enhances efficiency. Efficiency enhancement at 3-/6-dB power backoffs (PBOs) is obtained on the IQ complex plane to improve average efficiency. A single-transformer-footprint parallel-combining transformer (PCT) power combiner is implemented for compact die size. Fabricated in a 55-nm CMOS technology, the DPA is powered by 1.2-/2.4-V supply voltages and the core circuit only occupies 1.05 x 1.14-mm² chip area. It achieves 29.3-dBm peak output power with power added efficiency (PAE) of 43.1%. With 10-MHz 64-quadratic-amplitude modulation (QAM) local thermal equilibrium (LTE) signal, the DPA achieves ${P_{{avg}}}$ of 23.62 dBm and the average PAE of 24.4% with -25.6-dB error vector magnitude (EVM) at 0.85 GHz without using any digital predistortion (DPD) technique. Moreover, for 20-MHz 64-QAM wireless local area network (WLAN) signal, ${P_{{avg}}}$ of 21.01 dBm and the average PAE of 20.1% are obtained with -25.1-dB EVM.

A wideband Internet of Things (IoT) transmitter (TX) employing open-loop binary frequency-shift keying (BFSK) modulator with a pseudo-randomized phase transition (PRPT) time and a single-supply Class-G harmonic rejection (HR) power amplifier (PA) is presented. The proposed open-loop phase switching modulator eliminates the data-rate limitation in a conventional phase-locked loop (PLL)-based closed-loop modulator, while the PRPT scheme increases the effective phase resolution with a better power efficiency than delta-sigma modulation (DSM)-based randomization. Thus, a low spur level below -40 dBc is achieved with only a 4-bit phase resolution. The Class-G HR PA, including a four-level supply voltage waveform generator, is proposed as a high-efficiency and low spurious PA architecture. The proposed HR PA presents the third- and fifth-harmonics cancellation over the 0.3-to-1-GHz band, while only a single supply is required for Class-G implementation of the HR PA. The proposed BFSK TX is implemented in a 55-nm CMOS process. Measured with a 0.3-to-1-GHz continuous-wave carrier, TX output power and PA drain efficiency are 2.7 ± 0.2 dB and 52% ± 3%, respectively, operating from a 0.9-V supply. The HRs of -31.4/-42.7 and -28.2/-42.4 dBc at the third/fifth harmonics are measured at the lowest (0.3 GHz) and the highest (1 GHz) carrier frequencies, respectively. With a data rate of 1 Mb/s, the measured FSK errors are 3.6% and 4.2% at both ends of the operating frequency.

In this article, a high-efficiency broadband millimeter-wave (mm-Wave) integrated power amplifier (PA) with a low-loss slotline-based power combing technique is proposed. The proposed slotline-based power combiner consists of grounded coplanar waveguide (GCPW)-to-slotline transitions and folded slots to simultaneously achieve power combining and impedance matching. This technique provides a broadband parallel-series combining method to enhance the output power of PAs at mm-Wave frequencies while maintaining the compact area and high efficiency. As a proof of concept, a compact four-to-one hybrid power combiner is implemented in a 130-nm SiGe BiCMOS back-end-of-line (BEOL) process, which leads to a small die area of 126 μm x 240 μm and a low measured insertion loss of 0.5 dB. The 3-dB bandwidth is over 80 GHz covering the whole G-band (140-220 GHz). Based on this structure, a high-efficiency mm-Wave PA has been fabricated in the 130-nm SiGe BiCMOS technology. The three-stage PA achieves a peak power gain of 30.7 dB, 3-dB small-signal gain bandwidth of 40 GHz from 142 to 182 GHz, a measured maximum saturated output power of 18.1 dBm, and a peak power-added efficiency (PAE) of 12.4% at 161 GHz. The extremely compact power combining methodology leads to a small core area of 488 μm x 214 μm and an output power per unit die area of 662 mW/mm².

This article proposes a low-complexity frequency equalization technique for pulsewidth modulation (PWM)-residual-aliasing reduction in closed-loop Class-D audio amplifiers to achieve both low total harmonic distortion plus noise (THD+N) and low quiescent current. Based on the comprehensive analysis on the phase shift delay between the audio input and the loop filter's output for the prior PWM-residual-aliasing reduction technique, the proposed technique minimizes the non-idealities via a frequency-equalization path to enhance the cancellation ability of high-frequency PWM switching components. In this way, the PWM-residual-aliasing distortion is greatly suppressed, thereby permitting Class-D audio amplifiers to achieve a further-reduced THD+N for the entire audio band while operating at a low switching frequency ( $f_{SW}$ ), leading to less quiescent current consumption. Moreover, due to the minimized phase shift delay, the required bias current of the loop filter's first operational amplifier for the target THD+N can be reduced, resulting in even lower quiescent current. Compared with other state of the arts, this work's high-fidelity second-order Class-D audio amplifier, fabricated with cost-efficient 0.5-μm CMOS technology, not only achieves a competitive minimal THD+N of 0.00091% for a 1-kHz input as well as the lowest maximal THD+N of 0.0027% over the entire audio band while operating at a low $f_{SW}$ of 168 kHz but also features both the highest figure of merit (FOM) of 2536 and the lowest quiescent current of 0.4 mA, surpassing the prior arts by a factor of 2.3.

In this article, a Ka-band satellite communication (SATCOM) transceiver is first presented using a standard CMOS technology. The proposed Ka-band SATCOM transceiver consists of a high-linearity transmitter (TX) and dual-channel receiver (RX); both TX and RX are based on direct-conversion architecture. By implementing the dual-channel RX, multiple multiplexing modes, including polarization multiplexing and frequency multiplexing, can be enabled depending on the application. The RX variable gain is distributed in both RF blocks and baseband blocks to achieve a wide input dynamic range. The LNA employs a dual-coupling transformer for a low-noise figure (NF) and wideband input matching; moreover, it enhances the amplifier unilateralization characteristic to mitigate the loading effect from switched attenuators. An adjacent channel interference (ACI) cancellation scheme is proposed to further enhance the RX linearity in the frequency multiplexing mode. In the TX, single-turn high-quality-factor transformer is employed to realize matching network and four-way power combining. A prototype of the SATCOM transceiver is fabricated in a standard 65-nm CMOS process. Under 1.05-V supply voltage, the TX achieves a ${P{_{SAT}}}$ of 20.5 dBm and an average output power of 12 dBm with 2% error vector magnitude (EVM) and a 37.6-dB ACPR. The dual-channel RX achieves an NF of 5.4 dB, an IIP3 of -30 dBm on the high-gain mode, the ACI cancellation is measured of 7.9 dB with a 100-MHz signal bandwidth.

High common-mode rejection ratio (CMRR) of an analog front end (AFE) requires high intrinsic CMRR of the front-end amplifier with high input common-mode (CM) impedance. This article presents a common-mode replication (CM-REP) technique, which replicates the input CM voltage over the front-end amplifier. By eliminating the CM current flow and its mismatch effect, CM-REP improves CMRR and input CM impedance simultaneously. Implementation considerations regarding the input CM range, on-chip, and off-chip parasitics have been discussed with practical techniques incorporated with the proposed CM-REP. Fabricated in a 0.18-μm CMOS technology, the measured instrumentation amplifier (IA) exhibits >130-dB CMRR and 50-GΩ input CM impedance at 50/60 Hz concurrently. The >110-dB CMRR is achieved with input CM up to 900 mVpp and >102-dB total CMRR (TCMRR) is obtained with 1-MΩ || 10-nF mismatch of source impedance. The prototype consumes 1.86 μA from a 1.8-V supply and occupies an active area of 0.227 mm².

This work presents a 3-D-integrated opto-electrical receiver (RX) analog front end (AFE) operating up to 50 Gb/s. The electronic integrated circuit (EIC) is fabricated in ST SiGe BiCMOS-55-nm technology and flipped and mounted on top of the ST photonic integrated circuits (PICs) die through copper pillars (Cu-Pi). In the RX chain, a low-power fully differential shunt-feedback trans-impedance amplifier (FD SF-TIA) is exploited to reduce the input-referred noise. Following the TIA, a postamplifier (PA) based on a novel active feedback circuit topology extends the bandwidth (BW) and a buffer delivers the output electrical signal to the 100-Ω differential off-chip load. An automatic offset cancellation loop is included to protect the RX from any offset source at the input. The RX AFE consumes 56 mW from 1.8-V supply voltage and provides a trans-impedance (TI) gain of 78.7 Ω with 27-GHz BW. By exploiting the FD SF-TIA with low parasitic capacitance of the germanium photodiodes (Ge-PD) in the photonic die as well as BW recovery by the PA, the RX achieves the sensitivity of -7.5-dBm OMA at Ge-PD and -2.3-dBm OMA at the single-mode fiber (SMF) optical output with bit error rate (BER) of

A low-power 113-dB SNR, -93-dB total harmonic distortion (THD)+N, digital input Δ Σ-based filter-less Class-D amplifier for wireless headphone applications is presented. This performance is achieved by the following architecture improvements: 1) variable-frequency-Δ Σ Class-D with digital feed-forward and switching-frequency reduction, 2) common-mode-stabilized power stage, 3) current digital-to-analog converter direct drive, and 4) rotational first-order dynamic-element-matching techniques. It operates on a single 1.8-V power supply with no external passive components except for a supply decoupling capacitor. The Class-D headphone amplifier achieves 82-mW non-clipping output power with 93% efficiency at a 16-Ω and 33-μH load condition. The complete system was fabricated in a 40-nm CMOS process and occupies 1.33-mm² die area.

This article presents an adaptive zoom-capacitance-to-digital converter (CDC)-based CMOS humidity sensor. The humidity sensor is realized by means of two differential capacitors whose dielectrics are sensitive to humidity. The sensing capacitors are interfaced with a zoom CDC, which consists of a successive-approximation-register (SAR) analog-to-digital converter (ADC) and a 3rd-order delta–sigma modulator ( $\Delta \Sigma \text{M}$ ). The SAR ADC eliminates the influence of the baseline capacitance to reduce the input range of the $\Delta \Sigma \text{M}$ . To improve the energy efficiency of the CDC across the full input range, a power-aware floating inverter amplifier (FIA) array is proposed, which is configured based on the conversion results of the SAR logic. In addition, an adaptive range-shift (ARS) zoom CDC is proposed to: 1) resist off-chip parasitics and interference and 2) allow low redundancy and a more energy-efficient FIA-based comparator, thus reducing power consumption. The proposed CMOS humidity sensor is implemented in a 0.11- $\mu \text{m}$ CMOS process. Measurement results show a capacitance resolution of 17.9 aF and an effective number of bits (ENOB) of 14.0 within a conversion time of 1.01 ms. The proposed humidity sensor consumes 1.5 $\mu \text{W}$ of power and exhibits a 0.0094 % relative humidity (RH) resolution and a ±1.5 %RH peak-to-peak accuracy (3 $\sigma $ error of 5.5 %RH) among 12 chips from 20 to 85 %RH, and it achieves a figure of merit (FoM) of 0.135 pJ $\cdot $ %RH 2 , which is more than six times better than the state of the art.

Active load impedance variations in a phased array transmitter cause significant power amplifier (PA) performance degradation, in terms of output power, linearity, and power-added efficiency, which are key parameters to enable high-speed data throughputs using spectrally efficient modulation schemes. The system performance can be restored by using PAs having active or passive reconfigurability with the help of antenna impedance sensors. This article presents a low-power reflection-coefficient sensor for 5G millimeter-wave phased-array applications. The complex load impedance of the PA is determined based on the complex voltage over a sensing element, which can be integrated and co-designed with the PA output matching network, with minimal loss (

This article presents a millimeter-wave (mm-wave) Doherty-like load modulated balanced amplifier (LMBA) for high-speed wireless communication in a 28-nm bulk CMOS process. The presented architecture is based on a load modulation technique that injects an auxiliary signal into the isolation port a 90° power-combining hybrid coupler at the output stage. The injected signal thereby modulates the load impedance at the balanced ports that is seen by the two main power amplifiers (PAs). In contrast to a Doherty PA, both impedances are modulated in the same manner, either upward or downward, both resistively and reactively, without the need for a bandwidth limiting impedance inverter. Furthermore, there is no need for complex Doherty output matching structures, and hence, a low-loss hybrid can be used to modulate the load impedance. The auxiliary signal is generated using a Class-C auxiliary amplifier, producing an overall Doherty-like response. The presented architecture, which uses a single RF input and requires no additional baseband input signal or control signals, is able to achieve multi-Gb/s data rates up to 18 Gb/s. From the continuous-wave measurements, the amplifier demonstrates the power back-off (PBO) efficiency enhancement. At 36 GHz, the PA achieves a measured maximum power added efficiency (PAE) of 32% with 22.6-dBm saturated output power ( $P_{\text {sat}}$ ) and 30.5% PAE at a 19.6-dBm output referred 1-dB compression point (OP 1 dB ). At 6-dB PBO from $P_{\text {sat}}$ , the PA achieves a PAE of 24.2%. Modulated signal measurements were carried out using a single-carrier 64-quadrature amplitude modulation (QAM) signal at the center frequency of 36 GHz without digital pre-distortion (DPD). For a 64 QAM signal with a baud rate of 2 GSym/s (12 Gb/s), the PA achieves an average output power ( $P_{\text {avg}}$ ) of 16 dBm with a PAE avg of 22% with an EVM rms of −25 dB. Similar measurements were done using a 3 GSym/s signal, giving a data rate of 18 Gb/s, where the PA achieves a $P_{\text {avg}}$ of 15.5 dBm and PAE avg of 20% with an EVM rms of −25.1 dB.

To design noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs) with high resolution and good power efficiency, two key bottlenecks need to be addressed. One is to realize a high-order loop filter with low circuit overhead, and the other is to mitigate the thermal noise. This article presents an NS-SAR ADC that synergistically addresses both challenges. To achieve high-order efficiency, it proposes an innovative error feedback-cascaded integrator feedforward (EF-CIFF) structure that realizes third-order noise shaping using only a single amplifier. It combines the merits of both structures, showing improved robustness, and is free of dc offset concern. On reducing the kT/C noise, this work features a sampling kT/C noise cancellation (SNC) technique that reuses the native hardware of the EF-CIFF structure. An open-loop self-quenching floating-inverter dynamic amplifier (FIDA) is used to support all amplification with low noise and power. Prototyped in 65-nm CMOS, this work achieves 84.8-dB signal-to-noise-distortion ratio (SNDR) with 625-kHz bandwidth (BW) (OSR = 8) and 119 $\mu \text{W}$ , leading to 182-dB Schreier Figure of Merit (FoM). It uses only 0.8-pF input capacitance, which is $5\times $ smaller than prior NS-SAR ADCs with similar oversampling ratio (OSR) and SNDR.

For fast buffering of large stepwise input to an nF-range capacitive load, this article presents a 5-V rail-to-rail (RTR) input–output paralleled-amplifier (PA) in which a dynamic class-C amplifier (DCCA) and a linear single-stage operational transconductance amplifier (OTA) are combined in parallel. During slew time, the DCCA, which is designed to consume a near-zero static current, dominantly supplies the dynamic current up to 8.5 mA to the output. When the output gets closer to the fine-settling region, the DCCA is rapidly faded out in virtue of a dedicated near-zero dead-zone control (NDZC), and it hands over to the linear OTA. A current-redistributive RTR $G_{\text {m}}$ -boosting technique is also proposed so that the OTA can have a wide gain-bandwidth product (GBW) even over the RTR input range while minimizing the quiescent current dissipation. The prototype chip was fabricated only with 0.5- $\mu \text{m}$ 5-V CMOS devices, and it occupies a die area of 0.03 $\mu \text{m}^{2}$ . The proposed amplifier consumed a static current of 3.1 $\mu \text{A}$ with a supply voltage of 5 V. The slew rates (SRs) with load capacitances ( $C_{\mathrm {L}}$ ) of 0.8 and 10 nF were measured to be 10.3 and 0.86 V/ $\mu \text{s}$ , respectively, for a step input of $\Delta $ 4.2 V, which is a state-of-the-art result compared to prior chips. The measured GBW of 10–127 kHz was achieved over 0.8–10 nF $C_{\mathrm {L}}$ with ≥ 59° phase margin (PM). The measured GBW deviation in a common-mode voltage ( $V_{\mathrm {CM}}$ ) range of 0.3–4.7 V was within the maximum of 20%.

This article presents a quadrature switched/floated capacitor power amplifier (SFCPA) with deep back-off efficiency enhancement. The SFCPA is introduced to decrease the dynamic power consumption at power back-off (PBO), which could improve the system efficiency (SE). The reconfigurable self-coupling canceling transformer (RSCCT) with enhanced tuning range of turn ratio is used to achieve impedance boosting for further improved efficiency at deep PBO. Based on the proposed SFCPA, a watt-level quadrature digital power amplifier (DPA) with IQ cell sharing, hybrid Doherty, and impedance boosting is proposed for deep PBO efficiency enhancement. Implemented in 40-nm CMOS, the proposed DPA with 1.2-/2.4-V supply achieves 30.3-dBm saturated output power ( $P_{ out}$ ) with 36.6%/32.9%/29.1%/23.7%/18.6%/13.2% SE for 0-/3-/6-/9-/12-/15-dB PBOs at 2.4 GHz. For 60-MHz 256-QAM modulation signal, it delivers 23.32-dBm average output power ( $P_{ avg}$ ) with an error vector magnitude (EVM) of -31.9 dB and an average drain efficiency (DE) of 30.7%. For 40-MHz 1024-QAM signal, it shows 20.44-dBm $P_{ avg}$ with an EVM of -35.9 dB and an average DE of 22.6%.

This article reports the concept of a double maximum achievable gain (double- $G_{\mathrm{ max}}$ ) core for the implementation of sub-terahertz high-gain amplifier design. The double- $G_{\mathrm{ max}}$ core is a $G_{\mathrm{ max}}$ core that adopts another linear, lossless, and reciprocal network that satisfies the $G_{\mathrm{ max}}$ condition onto an even number of cascaded transistor-level $G_{\mathrm{ max}}$ cores. It is shown that the double- $G_{\mathrm{ max}}$ core, due to its regenerative nature, can achieve much higher gain per stage than that of the same number of cascaded $G_{\mathrm{ max}}$ cores while satisfying the unconditional stability. Implemented in a 65-nm CMOS process, by adopting the proposed double- $G_{\mathrm{ max}}$ core, 247- and 272-GHz two-stage amplifiers achieve the peak gain of 18 and 15 dB, the gain per stage of 9 and 7.5 dB, and the PAE of 4.44% and 2.37%, respectively, while dissipating 21.5 mW.

In this article, a 22.9–38.2-GHz dual-path noise-canceling low noise amplifier (LNA) is proposed, which can achieve a low noise figure (NF) by reducing the noise of both paths. Such LNA consists of one common gate (CG) amplifier with one three-stage transformer, one resistive feedback common-source (CS) amplifier, and two amplitude-adjusting amplifiers. The three-stage transformer is used in the CG amplifier to provide gain-boosting, noise-reducing, and wideband inter-stage matching operation, simultaneously. Meanwhile, amplitude-adjusting amplifiers with reconfigurable phase-tuning lines are utilized in both paths to optimize the noise-canceling performance. To verify the aforementioned principle, a dual-path noise-canceling LNA is implemented and fabricated using a conventional 28-nm CMOS technology. The proposed LNA consumed 18.9 mW under a 0.9-V supply. The measured NF is 2.65–4.62 dB within the operating frequency range of 22.9–38.2 GHz, while the peak gain is 14.5 dB. The in-band input 1-dB compression point (IP1 dB) and input third-order intercept point (IIP3) are −13.2 to −6.6 and −3.6 to 3.2 dBm, respectively.

A 24-GHz fully integrated frequency-modulated continuous wave (FMCW) direct conversion transceiver, implemented in a 55-nm low-power CMOS technology with a maximum $f_{\mathrm {T}}$ of 190 GHz in typical operating conditions and packaged in a 5-mm $\times $ 5-mm 32-lead quad-flat no-leads (QFN) package, is presented in this article. The single-chip transceiver uses a single 2.5-V supply while all the core circuits are powered by integrated regulators. The complex low-noise transductor in the receiver uses a quadrature hybrid to generate quadrature signals in the receiving front-end. The analog signal processing circuits including high-pass filters, low-pass filters, and programmable amplifiers are implemented following the receiver front-end circuitry. The FMCW signals are generated by an on-chip 24-GHz fractional-N frequency synthesizer. The synthesizer is completely integrated with the transceiver and provides built-in digital frequency modulation to generate chirping signals for the down-conversion local oscillator (LO) and the transmitted signals. The transmitter is composed of a balanced class-AB power amplifier driven by the FMCW signals from the frequency synthesizer.

The effect of gain and embedding of amplifying cells (amp-cell) on the output power of power amplifiers (PAs) at high mm-wave frequencies is studied. This is the frequency range where matching loss becomes comparable with the gain of the amp-cell in most silicon technologies. By deriving power equations of embedded amp-cell, power contours are plotted in the gain plane and an optimum embedding is designed to maximize the output power for a desired gain. To showcase the theory, a high-frequency, high-power amp-cell, called matched cascode, is introduced and subsequently embedded to boost both power gain and output power. To increase the output power even further, a differential slot power combiner (SPC) is introduced and its equivalent circuit is analyzed. Finally, using the embedded matched cascode cell, and the SPC, a $2 \times 8$ PA is implemented in 65-nm bulk CMOS. It consumes 732 mW from 2.4-V supply voltage, with a maximum power-added efficiency (PAE) of 1.03%. The PA features a $P_{\text {sat}}$ and OP1dB of 9.4 and 6.3 dBm, respectively, at 200 GHz, and a maximum power gain of 19.5 dB.

A novel architecture of a digital modulated polar phased-array transmitter with phase modulation (PM) phase-shifting and feed-forward controlled dynamic matching (FFCDM) is presented in this article. Phase-shifting in a PM signal path is utilized in each element, which shares many components including a phase modulator, baseband, and IF components. The characteristics of the proposed architecture are analyzed. With a constant envelope of PM signals, the implicit nonlinearity of the phase shifter in this architecture has low impact on the linearity performance of a phased-array system. Meanwhile, low phase error can be achieved by high-resolution phase interpolation with the digital predistortion (DPD) technique. Efficiency for both saturated and 6-dB back-off power is enhanced by digital power amplifier (DPA) with FFCDM. As a proof of concept, a 3–7 GHz 4-element phased-array transmitter is designed and fabricated in 40-nm CMOS based on the proposed method. The measured root-mean-square (rms) phase error of 0.3°, effective phase shifting resolution of 9-bit, and peak system efficiency of 38.2% are achieved. For 40 MHz 64-QAM modulation signal, it exhibits EVM of 5.38% and 5.37%, $P_{\text {out}}$ of 14.30 and 14.46 dBm, and PAPR of 7.08 and 6.97 at 3.5 and 5.2 GHz, respectively. The measured peak EIRP is 35.6 dBm with a unit antenna gain of 2.98 dBi at 5 GHz. The radiation patterns with 0°, 15°, 30°, and 45° steering are measured based on monopole antennas. Meanwhile, the array achieves < 4.7% and < 5.9% EVM for 64-QAM signals with bandwidths of 20 and 40 MHz, respectively.

This article presents a low-power fractional- ${N}$ all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, thus leading to lower jitter and settling time. The proposed ROS-PD adopts a bottom-plate sampling with a voltage zero-forcing technique, which yields high power efficiency and supports fractional phase compensation in the voltage domain through a programmable DAC. The PD output is then amplified by a low-noise gated amplifier and digitized by a low-power successive approximation register analog-to-digital converter (SAR-ADC). Leveraging the benefits of digital architecture, gain mismatches from the waveform estimator are calibrated by means of an LMS algorithm, consequently lowering fractional spurs. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 2.0–2.3-GHz carrier with an rms jitter of 414 fs while consuming only 1.15 mW. This corresponds to a state-of-the-art ADPLL FoMjitter of −247 dB in a fractional- ${N}$ mode. Due to the wide (largely linear) monotonic range and $4\times $ oversampling rate from a 48-MHz reference, without any additional circuitry, the proposed ADPLL can settle within $3~\mu \text{s}$ in face of a 70-MHz frequency step.

This article presents a fully integrated IEEE 802.11aj direct-conversion transceiver system in a 120-nm SiGe:C BiCMOS technology. The system includes a transmitter, a receiver, and two onboard substrates integrated waveguide-fed Yagi-Uda antennas. In the millimeter-wave frequency band, the common-mode (CM) signal in a transformer-based balun is a limiting factor for the linearity of differential devices. In this work, we analyze the cause of the CM effect and provide fast impedance equalization with a passive component compensation method to resolve this problem, which improves the linearity of the transmitter. A T-type second-order harmonic termination method is applied at the power amplifier (PA) output to further improve the linearity of the transmitter. The self-mixing method-based power detector is adopted at the output of the transmitter to have an accurate image signal and local oscillator (LO) leakage calibration. The transmitter reaches an output 1-dB compression point (OP1,dB) of 14.6-16.4 dBm and a conversion gain (CG) higher than 24 dB in the IEEE 802.11aj frequency band, operating from 42.3 to 48.4 GHz. The receiver achieves a 3.8-4.1-dB noise figure, -18.7- to -22-dBm input 1-dB compression point, and a CG better than 43.8 dB in the IEEE 802.11aj frequency band. In the system wireless data transmission test, the transceiver is fully compliant with the error vector magnitude (EVM) requirement of the IEEE 802.11aj standard up to the 64-quadrature amplitude modulation (QAM) operating mode, and the measured transmitter-to-receiver EVM is better than -28.5 dB at a 1-m distance over the IEEE 802.11aj frequency band. Compared to other states of the art, the transmitter's OP1,dB is the highest, and the demonstrated transceiver system delivers the highest performance in the IEEE 802.11aj wireless link.

This article proposes a multi-mode wireless transmitter for full-duplex (FD) and half-duplex (HD) operation based on a quadrature balanced switched-capacitor power amplifier (QB-SCPA) architecture in 65 nm CMOS. The QB-SCPA provides inherent passive transmit–receive (TX–RX) isolation along with an embedded digital self-interference cancellation (SIC) signal injection mechanism and exhibits excellent TX and RX linearity characteristics. To minimize noise figure degradation to the RX path, local oscillator (LO) signal sharing between the two SCPAs comprising the transmitter and a retiming circuit that generates the 25% clock signals is employed to obtain phase noise suppression at the LNA port. In the FD mode, 50 dB of SIC is demonstrated across the instantaneous bandwidth of a 20 MHz orthogonal frequency-division multiplexing (OFDM) signal with 11 dB peak-to-average power ratio (PAPR), along with −35 dB TX error vector magnitude (EVM) with SIC ON and without digital predistortion. The transmitter achieves a maximum output power of 23 dBm with 26.5% power-added efficiency (PAE) and 21 dBm with 17.4% PAE in HDTX and FD modes, respectively, and has a wide operating bandwidth between 1.5 and 3 GHz.

This article proposes a supply modulator (SM) that uses high switching frequency gallium-nitride (GaN) devices to achieve a four-phase fast step-down converter for the fast-tracking ability of the envelope tracking (ET). The ET signal is reshaped to generate an average power tracking (APT)-based signal to control the size of GaN switches to further increase light-load efficiency due to reduced switching loss. Moreover, a high-bandwidth and low-loss linear amplifier (LA) is used to supply the power amplifier (PA) to sufficiently provide fast-tracking speed for 5th generation (5G) NR ET. At a power of 3.5 W for 5G mobile phones, the peak efficiency that is tested with NR −130 MHz in the ET mode is as high as 85.7% over a wide load range.

Broadband active load-modulation power amplifiers (PAs) are effective to enable multistandard wireless communication systems with high dynamic-range wideband signals and high energy efficiency. Traditional Doherty or outphasing PA architectures support their classic active load-modulation operations but, however, exhibit limited carrier bandwidth. We propose a broadband active load-modulation PA architecture with multifrequency role-exchange coupler-based Doherty amplifier (MF-CDA) operations to cover over-an-octave bandwidth. A proof-of-concept PA has been designed and fabricated in a 45-nm RF CMOS SOI process, which achieves a peak PAE of 41.88%–19.4% with $P_{\mathrm {sat}}$ of over 22.66–19.53 dBm from 26 to 60 GHz. The PA also achieves a 33.75%–10.2% 6-dB PBO efficiency with its best 1.8 $\times $ efficiency enhancement over an ideal Class-B PA. Using a single-carrier 64-QAM signal with 0.8–3 GSym/S (4.8–18 Gb/s), the PA supports an average $P_{\mathrm {out}}$ of 15.8–11.3 dBm with an average PAE of 23.8%–8.5% at −23-dB rms EVM over the entire bandwidth. For a single-carrier 16-QAM signal with 1–2.5 GSym/S (4–10 Gb/s), the PA achieves an average $P_{\mathrm {out}}$ of 18.7–15.6 dBm with an average PAE of 34%–14.8% at $>-$ 20-dB rms EVM over the bandwidth. The PA also supports 5G NR modulation using 5G new radio (NR) FR2 200 MHz 1-CC 64-QAM signals, achieving 16.54%–5.2% average PAE at 12.25–9.34 dBm and average $P_{\mathrm {out}}$ with an rms EVM of −24 dB over 26–60 GHz.

In this article, we propose a bandgap reference (BGR) with a single bipolar junction transistor (BJT) branch and a proportional-to-absolute-temperature (PTAT)-embedded amplifier. Having fewer BJT and passive components, the proposed BGR uses less power and area compared to the conventional BGR that uses multiple BJTs and resistors. As the proposed BGR achieves temperature compensation by employing a feedback loop that has two gain stages, frequency compensation is required. We propose frequency compensation scheme where a compensation capacitor is connected between the BGR output and a current mirror node in the PTAT-embedded amplifier. By using this scheme, location of a mirror pole associated with the current mirror node can be optimized to achieve both improved stability and low power consumption. Fabricated in 0.18- $\mu \text{m}$ CMOS, the proposed BGR achieves temperature coefficient of 26.3 ppm/°C over −40 °C–140 °C; voltage accuracy ( $\sigma /\mu $ ) of 0.33%; and power supply rejection (PSR) of −52 dB, −44 dB at 100 Hz, 1 MHz respectively; while occupying 0.0082 mm2 and consuming 192 nW without startup circuit and trimming.

This article presents a scalable multiphase peak current-mode Buck controller with sub-milliohm direct current resistance (DCR) current sensing and synchronized overcurrent protection. Low DCR current sensing capability is critical in pursuing high efficiency and precise current balancing. For this purpose, a sub-milliohm DCR current sensing circuit is proposed. The low-frequency current signals from all the phases are amplified by a time-shared amplifier, and the outputs are combined with the exaggerated high-frequency signals, respectively, to rebuild the proportional current sensing signals. The small signal analysis and the design guidelines of the proposed sensing scheme are presented. The proposed current sensing scheme enhances the signal-to-noise ratio, improves the phase to phase current balancing, and dramatically reduces the silicon area of the sensing circuit. A latch-up problem of hiccup mode over current protection in the multi-chip parallel system is addressed in this article. A synchronized hiccup mode over current protection scheme is designed to solve the issue without adding extra communication bus to the system. The proposed controller is fabricated using a 0.6- $\mu \text{m}$ BiCMOS process, and the experimental results prove the effectiveness of the current sensing circuit and protection scheme.

This study describes the Ku -band 70- and 30-W-class internally matched gallium nitride (GaN) power amplifiers (PAs) for multi-carrier satellite communications (SatComs). The GaN PAs maintain low third-order intermodulation distortion (IMD3) over a wide offset frequency range of up to 400 MHz, whereas in the Ku -band, one PA can deliver a high peak output power of approximately 70 W and the other PA, a peak output power of higher than 30 W. To realize a wide offset frequency operation, our proposed output-matching circuit includes three different types of difference-frequency short circuits, two of which are embedded into a tournament-shaped output-matching circuit inside the PA package and the rest is embedded into the drain bias feed placed outside the package. To verify the short-circuit design and its effectiveness, two different power classes (70 and 30 W), Ku -band GaN PAs, were designed and fabricated, and then, their output transfer characteristics focusing on IMD3 were measured. The measurements show that the 70-W-class GaN PA achieves a peak output power of 48.6 dBm while maintaining a linear output power of over 40 dBm and an IMD3 of less than −26 dBc over wide offset frequencies ranging from 1 to 400 MHz. The 30-W-class GaN PA maintains a linear output power of over 36.3 dBm and an IMD3 of less than −27 dBc over wide offset frequencies of up to approximately 600 MHz. To the best of the authors’ knowledge, these PAs have a record output power level over a wide frequency range of 1–400 MHz or higher under the condition of a low IMD3 of less than −25 dBc, compared to previously reported Ku -band GaN PAs used for multi-carrier SatComs.

This article presents a wide input-range delay chain based time amplifier (TA) and its application to a 6.5-GHz digital fractional- $N$ phase-locked loop (PLL). The TA includes a delay-averaging linearity enhancement technique and the PLL is based on an improved dual-mode ring oscillator (DMRO) delta-sigma ( $\Delta \Sigma $ ) frequency-to-digital converter (FDC). The TA mitigates contributions to the PLL’s phase noise from DMRO flicker noise, which would otherwise degrade the PLL’s in-band phase noise, and from $\Delta \Sigma $ FDC quantization error, which would otherwise degrade the PLL’s phase noise at high bandwidth settings. This paper also presents a delay-free asynchronous DMRO phase sampling scheme, and the first experimental demonstration of a recently-proposed $\Delta \Sigma $ FDC digital gain calibration technique. The TA-assisted PLL achieves a random jitter of 145 fsrms, a total jitter that ranges from 151 to 270 fsrms as a result of fractional spurs, and a worst-case fractional spur of −49 dBc without requiring nonlinearity calibration.

High-speed, low-power optical interconnects, such as intensity modulation direct detection (IMDD) optical links, are increasingly deployed in data centers to keep pace with the growing bandwidth requirements. High-sensitivity low-power optical receivers (RXs) are the key components that enable energy-efficient IMDD optical interconnects. This article presents a low-power nonreturn-to-zero (NRZ) optical RX using a combination of a limited-bandwidth trans-impedance amplifier (TIA) and duobinary sampling to improve RX sensitivity at high data rates. Duobinary sampling leverages the well-controlled TIA inter-symbol interference (ISI) to recover the transmitted data, making it much more hardware efficient than canceling the ISI using a decision feedback equalizer (DFE). The proposed optical RX employs a CMOS-based analog front-end (AFE) to achieve high linearity and excellent power efficiency. Fabricated in 65-nm CMOS process, the prototype RX achieves optical modulation amplitude (OMA) sensitivity of −11.6 dBm at 16 Gb/s with 0.7-pJ/bit efficiency.

In this article, a dual-ramp modulation scheme is proposed to solve an instability during the discontinuous conduction mode (DCM) operation of current-mode constant on-time (COT) controlled boost converters. A duty cycle-dependent auxiliary waveform, which is generated by the proposed capacitor-coupled common-drain amplifier (CCCDA), is summed with an inductor current information to form a current feedback loop. With the proposed scheme, the pulse frequency modulation (PFM) operation can be spontaneously accompanied by the current-mode COT control to enhance a light-load efficiency. In addition, a translinear loop (TLL)-based valley current sensor is introduced to sense a valley inductor current while solving the response time and stability problems of the previous SenseFET-based current sensor. An adaptive ON-time (AOT) generator provides a quasi-fixed switching frequency in the CCM operation regardless of the conversion ratio. The proposed boost converter has been fabricated using a 0.18- $\mu \text{m}$ CMOS process with a total chip area of 1.23 mm $\times\,\,1.37$ mm. It achieves a peak efficiency of 94.5% even at a high-switching frequency of 10 MHz, and smooth mode transition between PFM and pulsewidth modulation (PWM) operations depending on the load conditions.

A $4\times $ interleaved pipelined ADC for direct-RF sampling applications is presented. It leverages the performance advantages of ring amplifiers to unlock greater architectural freedom. The first pipeline stage MDAC with a “passive-hold” mode eliminates the sub-ADC sampling path and associated problems. A high-speed ringamp topology employs digital bias control, robust common-mode feedback (CMFB), and an elegant self-resetting behavior. An asynchronous, event-driven timing control system improves several aspects of performance and enables fully dynamic power consumption and modular design re-use. A general technique is presented whereby the signal-to-distortion ratio (SDR) of any amplifier in the system can be measured in the background with an analog hardware overhead of only one comparator. In this amplifier-intensive architecture utilizing 36 ringamps, the 4-GS/s ADC fabricated in 16-nm CMOS achieves 62-dB SNDR and 75-dB SFDR at Nyquist, consumes 75 mW (including input buffer), and has a Walden figure of merit (FoM) of 18 fJ/conversion-step and a Schreier FoM of 166 dB, advancing the state of the art in direct-RF sampling ADCs by roughly an order of magnitude.

This article presents a broadband power amplifier (PA) with a distributed-balun output network that provides the PA optimum load impedance over a wide bandwidth. The proposed output network comprises two coupled-line sections and absorbs the device output capacitance. It employs a scalable coupled-line modeling approach that captures both the magnetic (inductive) and electric (capacitive) couplings between windings with fewer parameters and supports a rapid design process. Closed-form design solutions, design space limitations, bandwidth limits, and design tradeoffs are derived and analyzed comprehensively. Its extension to differential output and common-mode response is also discussed in detail. As a proof of concept, a prototype PA is implemented for multiband fifth-generation (5G) applications in 45-nm SOI CMOS. With no biasing retuning or network reconfiguration, the PA consistently achieves >19.1 dBm $P_{\mathrm {sat}}$ , >37.3% peak power-added efficiency (PAE), 17.8–19.6 dBm $P_{\mathrm {1dB}}$ , and 36.6%–44.3% PAE $_{P\mathrm {1dB}}$ over 24–40 GHz, verifying the truly wideband large-signal matching. The PA demonstrates 5G new radio (NR) frequency range 2 (FR2) modulation signals over 24–42 GHz, covering n257/n258/n260 5G bands. For 5G NR FR2 800-MHz 2-CC 64-QAM signals (11.78-dB PAPR), the PA achieves 11.3-dBm/16.6% average $P_{\mathrm {out}}$ /PAE with −25.1-dB rms EVM at 28-GHz and 10.2-dBm/13.6% average $P_{\mathrm {out}}$ /PAE with −25.1-dB rms EVM at 37 GHz.

This article reports a low-noise magnetic sensor front-end with an 18-bit Zoom ADC for detecting temporal magnetic nanoparticle (MNP) relaxation. Techniques such as dynamic element matching (DEM) and magnetoresistive correlated double sampling (MRCDS) are proposed to remove the sensor and analog front-end (AFE) 1/ ${f}$ noise while a fast-settling Miller compensation (FSMC) technique is proposed to reduce the amplifier power. Collectively, these result in state-of-the-art input-referred noise performance (9.7 nTrms) and a figure-of-merit (FoM) that is 6.6 $\times $ and 210 $\times $ better than previously reported magnetic sensor and relaxation-based AFEs, respectively. A relaxation-based magnetic immunoassay (MIA) was performed to demonstrate the concept. This design is implemented in a 0.18- $\mu \text{m}$ CMOS process and consumes 4.32 mW from a 1.8-V supply.

This article presents an efficient quadrature digital power amplifier (DPA) based on a complex-domain Doherty (CDD) architecture. The proposed CDD architecture allows a PA to achieve high efficiency through Doherty operation in a complex domain using two independent vectors with different amplitudes and phases. It demonstrates high efficiency when two vectors have in-phase components in the complex domain by introducing an additional efficiency peak. The proposed DPA based on a switch-capacitor PA (SCPA) employs the CDD and dual-supply Class-G techniques to enhance system efficiency (SE) and adds three additional efficiency peaks down to 12-dB power back-off (PBO). An additional efficiency peak at 6-dB PBO and two additional efficiency peaks at 2.5- and 12-dB PBOs are associated with CDD and Class-G, respectively. The prototype, fabricated in a 65-nm CMOS process, achieves 27.8-dBm peak output power ( $P_{\mathrm {OUT}}$ ) with a peak SE of 32.1%. It exhibits an error vector magnitude (EVM) of −42.0 dB (−43.3 dB) at a $P_{\mathrm {OUT}}$ of 14.7 dBm (15.4 dBm) for an 802.11ax 40-MHz (20-MHz) 1024-QAM OFDM signal with 13.1-dB (12.4-dB) peak-to-average power ratio (PAPR) at 2.2 GHz. The average SE measured with a 20-MHz single-carrier 1024-QAM signal with 6.8-dB PAPR at a $P_{\mathrm {OUT}}$ of 21 dBm is 18.4%.

This article presents a 6.78-MHz wireless power transfer system with a structure-reconfigurable power amplifier (SR-PA) and a 0X/1X regulating rectifier. The proposed 0X/1X regulating rectifier with local-loop control achieves voltage rectification and regulation without dc–dc converter usage to improve the receiver efficiency. To further enhance the system efficiency, the proposed SR-PA with global-loop power control adjusts its power-stage structure to realize adaptive power delivery. The transmitter and receiver chips were fabricated in a 0.25- $\mu \text{m}$ CMOS process using 5-V devices, and the resulting system was able to regulate an output voltage of 5 V. The measurement results demonstrated an 11.2% improvement in system efficiency for a light load and a 2.7 times increase in available output power compared with the same system without transmission power control. A measured peak receiver efficiency of 92.9% and a total system efficiency of 71.5% were also demonstrated.

This article presents a millimeter-wave (mm-wave) transmitter (TX) front-end employing a new inverse outphasing architecture with current-mode power amplifiers (PAs). This study on the conventional outphasing operation reveals its strong dependence on its voltage-mode driving source assumption and thus exhibits major limitations at mm-wave, since efficient and linear mm-wave PAs often behave as current sources. To address this challenge, we propose a current-mode inverse outphasing architecture that employs current-mode driving sources and is inherently compatible with mm-wave linear PAs. Moreover, the conventional series outphasing combiner is replaced by a much simpler and low-loss parallel power combining scheme. Closed-form mathematical expressions are derived for both the outphasing and inverse outphasing operations, including the active load modulation, Chireix compensations, and outphasing efficiency, which fundamentally explains the limitations of the conventional approach and the advantages of the inverse outphasing architecture. Further theoretical analysis discovers a circuit duality relationship between outphasing and inverse outphasing architectures, which offers unique circuit intuitions. As a proof-of-concept, we implement a 28-GHz TX front-end using cascode PAs, based on the inverse outphasing architecture. In the measurement, the TX achieves 22.7-dBm saturated output power with 42.6% PA drain efficiency. The TX exhibits effective PA efficiency enhancement at 6-dB power back-off (PBO), validating the high-efficiency inverse outphasing active load modulation. Modulation tests with high-order quadrature amplitude modulation (QAM) signals demonstrate that the TX supports >10-Gb/s high-fidelity complex signals and achieves the state-of-the-art modulation performance.

This article presents a successive approximation register (SAR)-assisted noise-shaping (NS) pipeline analog-to-digital converter (ADC) incorporating various techniques to improve its bandwidth (BW), energy efficiency, and robustness. A multiple-input dynamic amplifier is used for both residue amplification and error feedback (EF) summation, thus realizing a 1st-order NS with low power consumption. An additional residue feed-forward (FF) path is introduced in the 2nd-stage SAR ADC to compensate for the noise transfer function (NTF) deterioration caused by the gain mismatch in the multiple-input pairs of the dynamic amplifier. The partial-interleaving 1st stage breaks the speed bottleneck of the conventional three-phase timing arrangement, which significantly enhances the overall ADC’s speed and sampling performance. Besides, a coarse SAR ADC is introduced to further speed up the conversion with low power, while simultaneously enabling the enclosure of the data-weighted-averaging (DWA) on the DAC without a speed penalty. Finally, a low-cost inter-stage offset calibration is proposed that aligns the offset voltages among stages in the background without requiring an extra phase. Fabricated in the 28-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 75.2 dB over 40-MHz BW with only 7.5 over-sampling rate (OSR). Under a 1-V supply voltage, the ADC consumes 2.56 mW and exhibits a Scherier figure-of-merit (FoM) of 177.1 dB.

RF photonic components suffer from poor spurious-free dynamic range (SFDR) due to the high noise and distortion generated by a silicon photonic (SiP) Mach–Zehnder modulator (MZM). This work demonstrates a distributed silicon–germanium (SiGe) heterojunction bipolar transistor (HBT)-based low-noise amplifier (LNA) co-designed for linearization with a SiP MZM for a broadband radio-over-fiber (RoF) link. The SiGe LNA incorporates a distributed, tunable predistortion scheme that is inherently wideband and improves the third-order intercept point over an 18-GHz range. The assembled SiGe LNA and SiP MZM prototype demonstrates an SFDR as high as 120 ${\mathrm{ dB}}\cdot {\mathrm{ Hz}}^{2/3}$ at 9 GHz, a 14-dB improvement over previous SiP RF components or RoF links.

In this study, we examined a 120-GHz wideband I/Q receiver based on a baseband equalizing amplifier using 40-nm complementary metal oxide semiconductor (CMOS) technology. For low-power operation, the receiver chipset is integrated based on the direct conversion structure. To achieve high data-rate wireless communication, the receiver utilizes a frequency equalizing technique between the low noise amplifier (LNA)-mixer and baseband amplifier. With the proposed technique, the estimated overall bandwidth is increased as wider as 5 GHz. The 3-dB conversion gain bandwidth is 26 GHz, noise figure (NF) is 10.8 dB, and dc power consumption is 153.4 mW. For the dual-mode operation, the variable gain of the baseband amplifier is applied, and the conversion gain of the proposed receiver is 28.2 dB for the high gain mode and 14.8 dB for the low gain mode. The chip area of the receiver is 1.5 mm2. The proposed receiver exhibits a maximum data-rate of 12.5, 16, and 16 Gb/s for binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), and 16-quadrature amplitude modulation (16-QAM), respectively.