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The International Technical Program Committee (ITPC) of the IEEE International Solid-State Circuits Conference (ISSCC) selects outstanding articles from the papers presented at the conference and invites the authors to submit an extended manuscript to the Special Issue of IEEE Journal of Solid-State Circuits (JSSC). This November issue contains the selected papers from the Imagers, microelectromechanical systems (MEMS), and Displays (IMMD) and the Technology Directions (TD) sub-committees. Papers from Analog, Data Converters, Power Management, RF, and Wireless subcommittees are included in the December issue. Finally, the January issue will contain papers from Digital Architectures and Systems, Digital Circuits, Machine Learning, Memory, and Wireline subcommittees. [ABSTRACT FROM AUTHOR]

This Special Issue of the IEEE JOURNAL OF SOLID-STATE CIRCUITS presents a collection of the best papers selected from the 2022 IEEE International Solid-State Circuits Conference (ISSCC) that took place in a virtual format from 20 February until 24 February 2022. This issue covers articles from the RF, Wireless, Analog, Data Converters, and Power Management subcommittees. [ABSTRACT FROM AUTHOR]

This Special Issue of the IEEE Journal of Solid-State Circuits is dedicated to a collection of the best papers selected from the 2021 IEEE International Solid-State Circuits Conference (ISSCC) that took place on February 13-22, 2021, virtually. This issue covers papers from the Analog, Power Management, Data Converters, RF, and Wireless committees. [ABSTRACT FROM AUTHOR]

The International Technical Program Committee (ITPC) of the IEEE International Solid-State Circuits Conference (ISSCC) selects outstanding articles from the papers presented at the conference and invites the authors to submit a manuscript to the special issue of IEEE Journal of Solid-State Circuits (JSSC). The manuscripts offer extended materials such as in-depth circuit descriptions, more experimental results, and benchmarking data. The manuscripts subsequently undergo a rigorous review process. This November issue contains the selected papers from the Imagers, MEMS, and Displays (IMMD) and the Technology Directions (TD) subcommittees. Papers from Analog, Data Converters, Power Management, RF, and Wireless subcommittees are included in the December issue. Finally, the January issue will contain papers from Digital Architectures and Systems, Digital Circuits, Machine Learning, Memory, and Wireline subcommittees. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

This Special Issue of the IEEE Journal of Solid-State Circuits (JSSC) includes some of the highlights of the best papers presented at the 2020 Asian Solid-State Circuits Conference (A-SSCC), which was held on November 9–11, 2020. A-SSCC 2020 was originally planned to be held in Hiroshima, Japan. However, due to COVID-19, A-SSCC 2020 had to become a virtual conference. As one of the five conferences fully sponsored by the IEEE Solid-State Circuits Society, the A-SSCC was in its 16th appearance in 2020 since its inauguration in 2005 in Taiwan. Rotating among Asian countries, the A-SSCC is quickly becoming one of the leading global forums for the presentation of advances in solid-state circuits and system-on-a-chip (SoC). From 2018, this conference accepts field-programmable gate array (FPGA) papers for presentation and demo and allows two-page format papers for submission and publication. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable dc–dc converter for maximum thermoelectric generator (TEG) energy harvesting in a battery-powered duty-cycling wireless sensor node. The proposed dc–dc converter adopts discontinuous energy harvesting, which operates in single-input dual-output (SIDO) boost, battery-TEG pile-up buck (BTPB), dual-phase buck–boost (DPBB), and battery supplied buck modes with a single shared inductor. Fabricated in a 65-nm CMOS process, the converter adopts an adaptive dead-time controller for zero-voltage switching (ZVS) and an adaptive switch size (ASS) with maximum power point tracking (MPPT) to maximize efficiency in a wide TEG voltage range. The SIDO boost mode achieves 88.5% and 81.1% peak end-to-end efficiency with maximum and no-load conditions (only charging the battery), respectively. The combination of BTPB and DPBB modes to maximize the TEG power extraction during the battery-powered operation results in up to 44% saving in battery power. The battery-supplied buck mode achieves 93.3% peak efficiency. [ABSTRACT FROM AUTHOR]

The linearity of high-resolution current-steering digital-to-analog converters (DACs) is often limited by inter-symbol interference (ISI). While dynamic element matching (DEM) can be applied to convert a portion of the ISI to uncorrelated noise instead of nonlinear distortion, DEM alone fails to prevent ISI from at least introducing strong second-order nonlinear distortion. This paper addresses this problem by proposing, analyzing, and experimentally demonstrating a low-cost add-on technique, called ISI scrambling, that, in conjunction with DEM, causes a DAC’s ISI to be free of nonlinear distortion. The ISI scrambling technique is demonstrated in a 1-GS/s, 14-bit DEM DAC implemented in 90 nm CMOS technology. The DAC’s measured linearity is in line with the state-of-the-art and its measured output power spectra closely match those predicted by this paper’s theoretical results. [ABSTRACT FROM AUTHOR]

The development of security-aware mobile devices using wide-input–output (IO) nonvolatile memory (NVM) is hindered by high peak current, large area overhead for high read bandwidth (BWR), and considerable energy consumption for data movement between NVM and logic blocks. Furthermore, data stored in NVM are vulnerable to reverse-engineering attacks. This work presents a high BWR security-aware near-memory-computing spin-transfer torque magnetic random-access memory (STT-MRAM) macro using a multi-bit current-mode sense amplifier (MB-CSA) to reduce peak current and energy consumption for wide-IO access, a near-memory shift-and-rotate functionality (NSRF) in conjunction with the MB-CSA to reduce area overhead and enable the completion of read and logic operations within a single cycle, and a reverse-engineering-proof XOR–based memory data protector to protect data stored in NVM against reverse-engineering attacks. A 1-Mb 1024-b read STT-MRAM macro with data protector fabricated using foundry embedded 22-nm STT-MRAM. This work achieved 42.67 GB/s for BWR and 0.23 pJ/b. Inclusion of the NSRF circuit reduced area overhead by 33.3% while increasing latency by only 170 ps. [ABSTRACT FROM AUTHOR]

The Special Issue of the IEEE Journal of Solid- State Circuits (JSSC) includes some of the highlights of the best papers presented at the 2021 Asian Solid-State Circuits Conference (A-SSCC). This year, the A-SSCC 2021 is held as a hybrid conference on November 7–10, 2021 with attendees having the option to join the in-person meeting in Busan, Korea, or participate virtually through on-line platform. As one of the five conferences fully sponsored by the IEEE Solid-State Circuits Society, the A-SSCC was in its 17th appearance in 2021 since its inauguration in 2005 in Taiwan. Rotating among Asian countries, the A-SSCC is quickly becoming one of the leading global forums for the presentation of advances in solid-state circuits and system-on-a-chip (SoC). From 2021, only two-page format articles are allowed for submission and publication. [ABSTRACT FROM AUTHOR]

This article presents a 420-GHz phase imaging system designed in a 40-nm CMOS technology. It consists of a transmitter (TX), based on a multiplier chain, and a receiver (RX), based on a two-step IQ down-conversion. Those chips share an external, 17.5 GHz, reference to secure frequency synchronization between them. To increase the overall system signal-to-noise ratio (SNR), the TX is modulated with a low-frequency sine-wave signal, while a two-way LO power combining is implemented for the RX first mixer. Those techniques result in a measured TX effective isotropic radiated power (EIRP) of 10 dBm and RX noise figure (NF) of 27 dB, leading to the overall SNR of 52 dB (at a distance of 25 cm and a resolution bandwidth (RBW) of 100 kHz). Furthermore, the measured phase-detection root-mean-square (rms) $1\sigma $ precision is equal to 1.7° (on a 400 $\circ $ range, at a distance of 25 cm and processing time of 500 ns), which leads to 3.4- $\mu \text{m}$ range resolution. In addition, the system operation is illustrated in two imaging demonstrations, recognition of the printed text on paper and 3-D imaging. Those demonstrations illustrate the potential of the presented system and terahertz (THz) phase imaging in general. [ABSTRACT FROM AUTHOR]

This work introduces a bang-bang fractional- $N$ phase-locked loop with quantization noise shaping that overcomes the classical noise limit of a standard bang-bang phase detector. An adaptive algorithm, working in the background of the main system, guarantees optimal noise shaping across process and environmental variations. The prototype, implemented in a standard 28-nm CMOS process, has a core area of 0.21 mm2 and achieves an rms jitter (integrated from 1 kHz to 100 MHz) of 69.5 fs for integer- $N$ synthesized channels, 79.7 fs for typical fractional- $N$ channels, and 99.6 fs for near-integer fractional channels with a worst case fractional spur of −51.1 dBc. The power consumption is 10.8 mW, leading to a jitter-power figure of merit of −252.8 dB and −251.6 dB for integer- $N$ and fractional- $N$ channels, respectively. [ABSTRACT FROM AUTHOR]

This article presents a wideband $2 \times 12$ -bit direct-digital RF modulator (DDRM) operating in a 0.5-to-3-GHz band for 5G transmitters. The proposed digital Cartesian modulator features an advanced IQ-mapping technique to boost RF power by 3 dB and suppress the $I/Q$ image. To verify the proposed concept, a 40-nm CMOS prototype is implemented whose RF peak output power at 2 GHz is more than 14 dBm. It achieves an adjacent-channel leakage ratio (ACLR) of −52 dBc and an error vector magnitude (EVM) of −40 dB for a 20-MHz 256-QAM signal at 2.4 GHz. With a 320-MHz 256-QAM signal, the measured ACLR and EVM performances are better than −43 dBc and −32 dB at 2.4 GHz, respectively, without using any digital pre-distortion. [ABSTRACT FROM AUTHOR]

A primary advantage of antenna arrays is their spatial selectivity, which has been widely utilized to support various applications, such as beam-steering, blocker rejection, massive multi-in--multi-out (MIMO), targeting communication, radar, and imaging. In this article, we exploit and engineer this spatial selectivity in an MIMO array for directionally secured wireless communication. We propose constellation decomposition array (CDA) and spatial carrier aggregation (SCA) schemes to achieve high throughput keyless physical layer security using antenna arrays. In CDA, lower order quadratic-amplitude modulation (QAM) signals are fed into an MIMO array and are spatially combined in the target direction to realize desired higher order QAM signals but distort the modulation in unintended directions. In SCA, we feed different carriers to different elements in an MIMO array to perform spectral carrier aggregation spatially. In addition, we adopt temporal swapping to further enhance security by creating one-to-many symbol mapping in unintended directions. The concept is demonstrated on an eight-channel MIMO transmitter (TX) fabricated in 45-nm CMOS silicon on insulator (SOI) and on-board antenna array for over-the-air (OTA) measurements. Using four channels of the TX array in the CDA mode, an information beamwidth of 5°/10° is realized by spatially constructing a single carrier 64QAM signal using three QPSK signals or one QPSK signal plus one 16QAM signal with a total 64QAM data rate up to 3 Gb/s. Using SCA with two carriers of 64QAM signals and temporal swapping, an rms error vector magnitude (EVM) of 6.3% at broadside with an aggregated data rate of 1.2 Gb/s is achieved, in contrast to greatly distorted rms EVM of 10% at only 4° angle. [ABSTRACT FROM AUTHOR]

Active load impedance variations in a phased array transmitter cause significant power amplifier (PA) performance degradation, in terms of output power, linearity, and power-added efficiency, which are key parameters to enable high-speed data throughputs using spectrally efficient modulation schemes. The system performance can be restored by using PAs having active or passive reconfigurability with the help of antenna impedance sensors. This article presents a low-power reflection-coefficient sensor for 5G millimeter-wave phased-array applications. The complex load impedance of the PA is determined based on the complex voltage over a sensing element, which can be integrated and co-designed with the PA output matching network, with minimal loss (< 0.2 dB) and a negligible area penalty. A full-range phase detector with improved detection resolution is proposed, enabling an amplitude-insensitive phase detection. Fabricated in a 22 nm FD-SOI process, the sensor prototype occupies a silicon area of 0.024 mm2 and consumes 13.2 mW power. The sensor demonstrates a wide detection range with $\vert \Gamma \vert $ up to 0.7 (VSWR 5.67) in a load-pull test at 28 GHz. From $\Gamma $ circle of 0.2 up to 0.7, the maximum detection errors in the magnitude and phase of the $\Gamma $ are 0.14° and 40°, respectively. [ABSTRACT FROM AUTHOR]

This article presents a readout integrated circuit (ROIC) for capacitive touch-screen panels (TSPs) employing an amplitude-modulated multiple-frequency excitation (AM-MFE) technique. To prevent charge overflow, which occurs periodically at the beat frequency of the excitation frequencies, the ROIC modulates the amplitude of the excitation voltages at a mixing frequency derived from the excitation frequencies. Thus, the ROIC can sense the charge signal without charge overflow and maximize the signal-to-noise ratio (SNR) by increasing the amplitude of the excitation voltages up to the sensing range of the readout circuit. The proposed ROIC was fabricated in a 0.13- $\mu \text{m}$ standard CMOS process and was measured with a 32-in 104 $\times $ 64 touch-screen panel using 1 and 10 mm metal pillars. It reduces charge overflow up to 33.9 dB compared to operation without AM-MFE. In addition, the ROIC achieves a frame rate of 2.93 kHz, and SNRs of 41.7 and 61.6 dB with 1 and 10 mm metal pillars, respectively. [ABSTRACT FROM AUTHOR]

This paper introduces a novel class of architectures that unify true random number generation and private-key cryptography by reusing the cryptographic core for both tasks. The unified architecture is well suited for low-cost constrained secure integrated systems, in view of the inherent area efficiency and the low design effort entailed by conventional automated design flows. Clock pulse over-stretching in pulsed latch clocking generates randomness by inducing metastability and jittered oscillations. Shannon confusion and diffusion in the cryptographic datapath enforce high entropy and robustness against variations. Conventional cryptographic operation is alternatively performed at moderate clock pulsewidths. A 40-nm CMOS testchip demonstrates the proposed unified architecture with a compact area of 0.43 $\cdot 10^{6}~F^{2}$ ($F\,\,=$ minimum feature size), based on a SIMON cryptographic core. The true random number generator (TRNG) output shows cryptographic-grade quality without any calibration across dice, process (across two manufacturing lots), voltage, and temperature variations. Energy per encryption down to 0.25 pJ/bit is demonstrated. Unification of TRNG and the cryptographic core results in inherent data locality and obfuscation of key generation within logic, improving the resilience to physical attacks. [ABSTRACT FROM AUTHOR]

This article proposes a supply modulator (SM) that uses high switching frequency gallium-nitride (GaN) devices to achieve a four-phase fast step-down converter for the fast-tracking ability of the envelope tracking (ET). The ET signal is reshaped to generate an average power tracking (APT)-based signal to control the size of GaN switches to further increase light-load efficiency due to reduced switching loss. Moreover, a high-bandwidth and low-loss linear amplifier (LA) is used to supply the power amplifier (PA) to sufficiently provide fast-tracking speed for 5th generation (5G) NR ET. At a power of 3.5 W for 5G mobile phones, the peak efficiency that is tested with NR −130 MHz in the ET mode is as high as 85.7% over a wide load range. [ABSTRACT FROM AUTHOR]

This article presents a wide input-range delay chain based time amplifier (TA) and its application to a 6.5-GHz digital fractional-N phase-locked loop (PLL). The TA includes a delay-averaging linearity enhancement technique and the PLL is based on an improved dual-mode ring oscillator (DMRO) delta-sigma (ΔΣ) frequency-to-digital converter (FDC). The TA mitigates contributions to the PLL’s phase noise from DMRO flicker noise, which would otherwise degrade the PLL’s in-band phase noise, and from ΔΣ FDC quantization error, which would otherwise degrade the PLL’s phase noise at high bandwidth settings. This paper also presents a delay-free asynchronous DMRO phase sampling scheme, and the first experimental demonstration of a recently-proposed ΔΣ FDC digital gain calibration technique. The TA-assisted PLL achieves a random jitter of 145 fsrms, a total jitter that ranges from 151 to 270 fsrms as a result of fractional spurs, and a worst-case fractional spur of −49 dBc without requiring nonlinearity calibration. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

I Would like to thank the Solid-State Circuits Society (SSCS) leadership and Administrative Committee for appointing me as the new Editor-in-Chief (EiC) of the IEEE Journal of Solid- State Circuits (JSSC). It is both a great honor and opportunity to lead the flagship SSCS journal. I want to additionally thank the outgoing EiC Prof. Pavan Hanumolu of University of Illinois at Urbana–Champaign, who has been very helpful in the transition this year. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

This Special Issue of the IEEE Journal of Solid-State Circuits (JSSC) features a Special Section on key invited papers presented at the 2021 Radio Frequency Integrated Circuits Symposium (RFIC Symposium), held in hybrid mode on June 6–8 (in-person) and June 21–July 20, 2021 (online). The RFIC Symposium is the world’s premier conference focused on RF and millimeter-wave (mm-wave)-integrated circuits and systems technology. It shares the venue with the IEEE MTT-S International Microwave Symposium (IMS) as part of the Microwave Week and is co-sponsored by the IEEE Solid-State Circuits Society. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

This article presents a 5-GS/s continuous-time (CT) multi-stage noise-shaping (MASH) analog-to-digital converter (ADC). The ADC consists of three first-order modulators with a 3-bit quantizer/digital-to-analog converter (DAC) per stage. An RC-hybrid stabilization DAC is used to compensate for the excess loop delay and excess phase shift. A delay matching all-pass input filter with a low-pass feedforward filter is employed to suppress input signal leakage. As a result, inter-stage DACs are waived in residue generation, and low-power, area-saving Gm-C integrators are enabled in the back-end stages. The MASH ADC was implemented in 40-nm CMOS and occupies 0.21 mm2. The ADC achieves 68-dB dynamic range (DR) and 65-dB signal-to-noise and distortion ratio (SNDR) over a 360-MHz bandwidth (BW). The ADC consumes 158 mW from 1/1.1/1.8 V supplies, yielding 159-dB Schreier figure-of-merit (FOM) and 151-fJ/Conv. Walden FOM. [ABSTRACT FROM AUTHOR]

This article presents a third-order voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) that leverages pseudo-virtual ground (PVG) feedforwarding (FF), linearizing the VCOs and enabling higher order noise shaping with a single feedback digital-to-analog converter. This technique leads to a power-efficient ADC implementation with a wide dynamic range. The ADC is fabricated in a 65-nm process and achieves a 92.1-dB SNDR in a 2.5-kHz bandwidth. This results in a state-of-the-art 179.6-dB figure-of-merit (FoM) among previously published VCO-based ADCs. The PVG FF technique allows the ADC to attain extremely high linearity, 123-dB peak SFDR, with a wide 1.8-Vpp differential input range. The ADC maintains performance with up to 200-mV variation on the 0.8-V supply and across temperatures from 0 to 70 °C. [ABSTRACT FROM AUTHOR]

This article introduces a power-efficient 24.25– 71-GHz multi-band phased-array receiver supporting all allocated fifth-generation mobile network new radio (5G NR) frequency range 2 (FR2) bands at 24/28/39/47 GHz and the potential 5G NR-U bands in unlicensed 57–71 GHz. A novel harmonic-selection technique is introduced to extend the operating bandwidth with low power consumption. By switching between the fundamental-selected mode, the second-harmonic-selected mode, and the third-harmonic-selected mode, only signals in the desired bands can be preserved, while the unselected mixing components are rejected. A dual-mode multi-band low-noise amplifier (LNA) based on a configurable transformer is adopted to realize broadband operation with minimized power consumption and noise figure (NF). The Hartley architecture is employed to further improve the image rejection performance. A hybrid-type polyphase filter (PPF) with a detector-based high-precision calibration block is utilized in this work to realize the Hartley operation with reduced insertion loss (IL). The proposed phased-array receiver is fabricated in a standard 65-nm bulk CMOS process. With the concerted efforts of all components, the proposed multi-band receiver can support 5G standard-compliant OFDMA-mode modulated signals up to 256QAM with a 400-MHz channel bandwidth from 24 to 71 GHz. Better than 36-dB inter-band blocker rejections can be maintained by this work. With existing of 0-dBc inter-band blockers at worst case frequencies, this receiver shows EVMs of −33.3, −30.9, −31.6, and −28.5 dB at 28, 39, 47.2, and 60.1 GHz, respectively. The power consumptions for a single receiver channel are 36, 32, 51, and 71 mW at 28, 39, 47.2, and 60.1 GHz, respectively. [ABSTRACT FROM AUTHOR]

A low-noise synthesizer design in the millimeter-wave (mm-wave) range is complicated by the invariably large closed-loop gain and the high operation frequency of the voltage-controlled oscillator (VCO). To overcome these challenges, this work proposes a harmonic-mixing synthesizer system with a 188-dB figure-of-merit mm-wave VCO. The synthesizer extends the bandwidth to 5 MHz, thereby suppressing VCO noise. Importantly, DSM is not amplified by the $f_{\mathrm{ VCO}}/f_{\mathrm{ ref}}$ gain of the system. A prototype employing a 74-MHz reference achieves a −250-dB phase-locked loop (PLL) figure of merit with a measured 88-fs rms jitter. [ABSTRACT FROM AUTHOR]

This article presents a $D$ -band Doherty power amplifier (PA) featuring a low-loss and compact slotline-based eight-way power combiner to improve the saturated output power and power back-off (PBO) efficiency. The proposed combiner consists of grounded coplanar waveguides (GCPWs), slotlines, and SLOT-GCPW coupling structures. Instead of the conventional transformer structure, the proposed SLOT-GCPW coupling structure effectively reduces insertion loss, increases the common-mode rejection, and encounters a comfortable symmetrical compact layout. More importantly, the proposed combiner can also be applied to achieve impedance inverters for active load modulation in a compact size. Based on the proposed multiway combining Doherty PA prototype, a high-efficiency and high-output $D$ -band PA is implemented in a 130-nm SiGe bipolar CMOS (BiCMOS) with ${f_{t}/f_{\max }}$ of 350/450 GHz. The extremely compact power combiner leads to a small PA core area of $1.1 \times 0.53$ mm2. The PA achieves a peak small-signal gain of 21.8 dB with 3-dB bandwidth from 107 to 135 GHz. At 110/120/130 GHz, the PA achieves 22.7/22.6/22.4 dBm ${P_{\mathrm{ sat}}}$ with 18.7%/17.2%/16.1% peak power-added efficiency (PAE) and 12.1%/11.7%/9.8% PAE at 6-dB PBO from ${P_{\mathrm{ sat}}}$. Modulation measurement with single-carrier 16-quadrature amplitude modulation (QAM) and 64-QAM signals has been performed. For a 2-GHz 16-QAM signal, the PA achieves 13.74 dBm ${P_{\mathrm{ avg}}}$ and 7.88% average collector efficiency with 11.6% error vector magnitude (EVM) at 131.5 GHz. The PA also supports a 2-GHz 64-QAM signal, achieving 13.76 dBm ${P_{\mathrm{ avg}}}$ and 7.92% average collector efficiency with 11.9% EVM at 131.5 GHz. [ABSTRACT FROM AUTHOR]

This article presents a BJT-based CMOS temperature sensor with a wide sensing range from −50 °C to 180 °C. To effectively relax the sensor resolution requirement and conversion time over the entire temperature range to improve energy efficiency, we introduce a nonlinear subranging readout scheme together with double sampling to achieve dynamic reconfiguration of the sensor readout according to the ambient temperature. We further reduce the sensor power at high temperature by devoting the $\beta $ -cancellation circuit only for BJT biasing while applying a temperature-independent bias current for the other sensor building blocks. Implemented in 0.18- $\mu \text{m}$ CMOS with four-wire connections and switch-leakage compensation based on small BJTs, the proposed sensor chip prototype achieves a high resolution-FoM of 7.2 pJ $\cdot \text{K}^{{2}}$ at 150 °C, while featuring a small sensing error of ±0.45 °C under a 1.5-V supply. [ABSTRACT FROM AUTHOR]

A 12V/24V-to-1V pulsewidth modulation (PWM) controlled double step-down (DSD) power converter with delay-insensitive and dual-phase charging techniques is presented. The proposed PWM controller has two feedback loops to regulate the output voltage and the voltage across the flying capacitor, respectively. With the proposed delay-insensitive technique, near-optimal transient responses are achieved by using the PWM control regardless of the time of occurrence of the transient. Moreover, the responses are further improved by two times by using the proposed dual-phase charging technique. The converter was fabricated in a 0.18- $\mu \text{m}$ BCD process with all power transistors integrated on chip. For 12V-to-1V conversion and 24V-to-1V conversion, the measured peak efficiencies at 1-MHz switching frequency are 88.3% and 83.5%, respectively. With a load current step of 3 A and a rise time of 20 ns, the measured voltage droop and 1% settling time are 56 mV and 0.9 $\mu \text{s}$ , respectively. [ABSTRACT FROM AUTHOR]

In this article, a 6-GHz, 2-bit, fourth-order continuous-time delta–sigma (CT $\Delta \Sigma $) analog-to-digital converter (ADC) fabricated in 28-nm CMOS is presented. It achieves −101- and −105-dBc total harmonic distortion (THD)/third-order inter-modulation (IM3) typically and 72.3-dB signal to noise and distortion ratio (SNDR) in 120-MHz bandwidth (BW). The ADC comprises four cascaded integrators with inverter-based amplifiers, an offset compensated 2-bit quantizer, and calibrated 2-bit feedback (FB) digital-to-analog converter (DAC). The DAC and quantizer employ blind digital calibration techniques enabling the wideband linearity performance. The ADC does not require any external test signal during calibration. The power dissipation of the modulator core, including demultiplexer, is 108.8 mW. [ABSTRACT FROM AUTHOR]

This article presents a fully integrated multi-phase (MP) buck converter for on-chip power management units. A peak-and-valley differential sensing (PVDS) scheme based on a flying capacitor is proposed to evenly balance the multiple inductor currents without significant power overhead even under mismatches in inductances, parasitic series resistances, and control-signal skews among phases. In addition, dynamic re-allocation of on-chip capacitors enables an even more optimal frequency response and output ripple based on the number of activated phases. It also improves the chip area efficiency, resulting in a higher power density. The proposed DLL-based MP clock generation provides high granularity in the phase-shedding control to achieve high efficiency over a wide load range. The proposed fully integrated buck converter using six bond-wire inductors (1 nH) was fabricated in a 28-nm CMOS process. The chip running at a frequency of 400 MHz/phase can finely adjust the number of active phases by an integer step ranging from 1 to 6 through sensing a load current. A maximum power density of 1.23 W/mm2 and a peak efficiency of 83.7% were measured. This work achieved an ultra-fast dynamic voltage scaling (DVS) rate of 75 mV/ns. [ABSTRACT FROM AUTHOR]

This article reports an ultra-low-power (ULP) Bluetooth low-energy (BLE) receiver with an improved spurious-free dynamic range (SFDR). It features two passive-intensive RF techniques: an $N$ -path passive balun-LNA and a pipeline down-mixing baseband (BB)-extraction scheme. They together offer a high- $Q$ bandpass response at RF, and a high passive gain to suppress the noise of the BB hybrid complex filter. Specifically, the balun-LNA is a step-up triple-coil transformer aided by an $N$ -path switched-capacitor (SC) network to perform in-band voltage amplification, high- $Q$ bandpass filtering, $I/Q$ down-mixing, and input-impedance matching. Instead of using active amplifiers as the first-BB gain stage, we passively extract the four-phase ($I/Q$ and differential) BB signals using a pipeline of passive-SC networks that can stack up the voltage gain. Prototyped in TSMC 28-nm CMOS, the BLE receiver consumes only 266 $\mu \text{W}$ , of which 75 $\mu \text{W}$ in the BB hybrid filter at 1 V, and 191 $\mu \text{W}$ in the LO divider + buffer at 0.6 V. Measured at the maximum RF-to-BB gain of 61 dB, the receiver exhibits a noise figure (NF) of 6.1 dB and an out-of-band (OOB)-IIP3 of 22.5 dBm. The corresponding SFDR is 77 dB for a 1-MHz BLE channel and a 10-dB minimum signal-to-noise ratio (SNR $_{\mathrm {min}}$). The OOB-B−1 dB is −3 dBm. [ABSTRACT FROM AUTHOR]

We present design techniques for single-bit continuous-time delta–sigma modulators that attain high resolution (>16 bits) over a bandwidth (BW) that is more than ten times the audio range. We introduce the zapped, virtual-ground-switched dual return-to-open DAC which is immune to ISI and other transition-dependent errors. FIR feedback facilitates chopping, improves clock-jitter sensitivity and the loop filter’s linearity. We show that the compensation FIR DAC, which is typically bulky, can be implemented in an extremely power- and area-efficient manner in a single-bit modulator using a capacitive DAC and passive summation. Thanks to these techniques, the fabricated prototype achieves 103.2-/104.3-dB signal to noise and distortion ratio (SNDR)/signal to noise ratio (SNR) in a 250-kHz bandwidth while operating at 48 MS/s. Consuming 17.7 mW from a 1.8-V supply, the modulator occupies 1.1 mm 2 in a 180-nm CMOS process. The Schreier (SNDR) figure of merit (FoM) is 174.7 dB. [ABSTRACT FROM AUTHOR]

Standard-cell-based memory (SCM) circuits with fully digital signals are attractive for power-/energy-constrained edge devices due to the strong voltage scaling capability, fast design iteration, and flexibility in integration. In this article, a 13-transistor (13T) static-random access memory (SRAM) circuit with ultra-wide range voltage scaling capability is proposed for ultra-low-power applications. By adopting the concept of SCM, the 13T SRAM cell is custom-designed, while providing fully digital inputs and outputs. Without any analog circuitry, the 13T memory array is fully synthesizable and compatible with the commercial semi-custom design flow. A specialized circuitry is employed in the 13T SRAM cell to enable cell-level bit-interleaving. An 8-kb 13T SRAM bank is fabricated in the UMC 55-nm low power CMOS technology, achieving an area density of $5 \mu \text{m}$ 2/bit. The minimum operational voltage for the 13T SRAM circuit is 324 mV, while the data retention voltage is down to 279 mV. The 13T SRAM circuit achieves the minimum energy point at 0.4 V for both the read (32.8 fJ/bit) and write (54.1 fJ/bit) operations, providing a good opportunity to perform voltage scaling together with logic blocks when embedded in the same power domain. [ABSTRACT FROM AUTHOR]

In this work, we present a novel 8T static random access memory (SRAM)-based compute-in-memory (CIM) macro for processing neural networks with high energy efficiency. The proposed 8T bitcell is free from disturb issues thanks to the decoupled read channels by adding two extra transistors to the standard 6T bitcell. A 128 $\times $ 128 8T SRAM array offers massively parallel binary multiply and accumulate (MAC) operations with 64 $\times $ binary inputs (0/1) and 64 $\times $ 128 binary weights (+1/–1). After parallel MAC operations, 128 column-based neurons generate 128 $\times $ 1–5 bit outputs in parallel. The proposed column-based neuron comprises 64 $\times $ bitcells for dot-product, 32 $\times $ bitcells for analog-to-digital converter (ADC), and 32 $\times $ bitcells for offset calibration. The column ADC with 32 $\times $ replica SRAM bitcells converts the analog MAC results (i.e., a differential read bitline (RBL/RBLb) voltage) to the 1–5 bit output code by sweeping their reference levels in 1–31 cycles (i.e., $2^{N}$ –1 cycles for $N$ -bit ADC). The measured linearity results [differential nonlinearity (DNL) and integral nonlinearity (INL)] are +0.314/–0.256 least significant bit (LSB) and + 0.27/–0.116 LSB, respectively, after offset calibration. The simulated image classification results are 96.37% for Mixed National Institute of Standards and Technology database (MNIST) using a multi-layer perceptron (MLP) with two hidden layers, 87.1%/82.66% for CIFAR-10 using VGG-like/ResNet-18 convolutional neural networks (CNNs), demonstrating slight accuracy degradations (0.67%–1.34%) compared with the software baseline. A test chip with a 16K 8T SRAM bitcell array is fabricated using a 65-nm process. The measured energy efficiency is 490–15.8 TOPS/W for 1–5 bit ADC resolution using 0.45-/0.8-V core supply. [ABSTRACT FROM AUTHOR]

This article presents design techniques for a PAM-4 baud-rate digital clock and data recovery (CDR) circuit utilizing a stochastic phase detector (SPD). The proposed baud-rate phase detector (PD) is designed in an inductive and stochastic way, so there is a clear difference from the existing deductive and logical method used in sign-sign Mueller–Müller PD (SS-MMPD), a representative baud-rate PD. By collecting the histograms of the sequential PAM-4 patterns under EARLY and LATE sampling phases and calculating optimal weights, the SPD exhibits optimized phase-locking characteristic that maximizes the PAM-4 vertical eye opening (VEO) compared with the conventional logical approaches. In addition, unlike SS-MMPD, which may suffer from a severe multiple-locking problem, the SPD tracks a unique and optimal sampling phase even with an adaptive decision-feedback equalizer (DFE). For verification, a prototype PAM-4 receiver is fabricated in 40-nm CMOS technology and occupies 0.24 mm2. Tested with PRBS-7 patterns, it achieves a bit error rate (BER) of less than $10^{-11}$ and energy efficiency of 2.4 pJ/b at 48 Gb/s. [ABSTRACT FROM AUTHOR]

With the widespread of deep neural networks (DNNs) in diverse applications, tiny platforms such as Internet-of-Things devices are starting to adopt DNNs. Due to their extreme energy and form factor constraints, conventional digital-only implementations of multiply-and-accumulate (MAC) acceleration faced fundamental limitations. To that end, the investigation into mixed-signal computing architectures is growing rapidly. Motivated by the flash ADC, this article proposes FlashMAC architecture that can natively support multibit multiplication. In addition, through fusing time- and frequency-domain computing methods without power-hungry oscillators, it enables low latency accumulation with low power consumption. As a result, the proposed time-frequency hybrid architecture achieves high energy efficiency with the support for complex DNN models requiring higher precision. To enhance the robustness of PVT variation of the mixed-signal architecture, a frequency calibration loop is integrated. In addition, motivated by the data-dependent performance of the FlashMAC architecture, variable latency-aware scheduling is proposed. The FlashMAC does not skip MAC operations as zero-skipping architectures do, but the latency of the operation can be lower when operands are smaller in magnitude. Tackling the issue through software and hardware co-optimization, loose synchronization architecture and magnitude-aware weight reordering increase the DNN benchmark performance by achieving higher utilization of the parallel FlashMAC array. The proposed features are integrated into a test chip which is fabricated in 65-nm logic CMOS technology. The silicon chip achieves 56.52 TOPS/W peak energy efficiency and a peak operating frequency of 90 MHz. Tested with the VGG16 benchmark trained on the Imagenet dataset, it achieved 17.04-ms latency while showing 11.15 TOPS/W energy efficiency. As a result, compared to the previous state-of-the-art, the proposed FlashMAC achieved 3.15 $\times $ higher normalized energy efficiency. [ABSTRACT FROM AUTHOR]

Terahertz (THz) beamforming arrays are critical to address emerging applications in wireless communication, sensing, and imaging. Enabling such architectures, particularly with respect to synchronization of distributed radiating THz sources, is very challenging due to the sensitivity of such synchronizations to variations of process, voltage, temperature (PVT), and device mismatches. In this article, we propose and demonstrate a multi-layer THz array architecture to address robust frequency synthesis, optimal harmonic THz power generation, and scalable phase generation for THz beamforming. The bottom-most layer of this multi-layer network consists of a scalable 2-D negative transconductance (−Gm) cells that collectively oscillates at the center frequency of 69.3 GHz, thereby establishing a robust frequency and phase distribution across the entire chip. By eliminating independent oscillation capability of each node and merging resonator and coupling structures into one single network, the 2-D mesh removes the possibility of moving out of synchronization due to PVT variations or device mismatches and forms the underlying frequency synthesis layer. Local frequency multiplication and radiating elements are placed across the 2-D THz array, and beamforming is enabled through varactor control in the $-G_{m}$ cells. We demonstrate the proposed architecture in a $4\,\times \,4$ array with effective isotropic radiation power (EIRP) of +14 dBm at 0.416 THz in a lensless setup using a 65-nm CMOS process with the beamforming capability of ±30° in both ${E}$ - and ${H}$ -planes. [ABSTRACT FROM AUTHOR]

This article presents a continuous-time (CT) delta–sigma ($\Delta \Sigma $) capacitance-to-digital converter (CDC) intended for use in applications with high capacitance resolution (tens of aF), and a large parasitic capacitance ${C}_{P}$ ($>$ 400 pF). It consists of a current conveyor (CC) front-end and a CT $\Delta \Sigma $ modulator. The CC-based front-end isolates ${C}_{P}$ from the first integrator of the modulator, and the CC’s output current is directly coupled to the CT $\Delta \Sigma $ modulator. The CC uses a class-AB configuration, which enables to maintain energy efficiency and its capacitance resolution even with ${C}_{P}$. The proposed CDC is fabricated in a 110-nm CMOS process and occupies only 0.033 mm2. It achieves a capacitance resolution of 21.5–59 aF with an input range of 0.2–1.5 pF. This corresponds to an effective resolution of 14.3 bits in a conversion time of 1.2 ms, while drawing only 120 $\mu \text{W}$ from a 1.5-V supply. It also achieves a capacitance resolution of 119.4 aF with ${C}_{P}$ of 480 pF, offering robust capacitance resolution with external noise interference (10 ${V}_{\text {PP}}$). [ABSTRACT FROM AUTHOR]

This Special Section of the IEEE JOURNAL OF SOLID- STATE CIRCUITS (JSSC) features expanded versions of key invited papers that were presented at the 2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), which was held virtually on November 16–19, 2020. [ABSTRACT FROM AUTHOR]