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The functional split-gate type trigate flash memory cell transistors have successfully been fabricated for the first time, and their threshold voltage (Vt) variations before and after NOR-mode program/erase cycle have systematically been compared with the stack-gate ones. It was experimentally found that split-gate type cell transistors with the same control gate length (LCG) of 176 nm show much smaller Vt distribution after erase compared to those of stack-gate ones. Moreover, the measured source-drain breakdown voltage (BVDS) is higher than 3.1 V even the LCG was down to 76 nm. This indicates that the developed split-gate type trigate flash memory is very effective for scaled NOR-type flash memory with highly suppressed over-erase.

Variability of TiN FinFET performance is comprehensively studied. It is found that the variation of the in the FinFET occurs and the standard deviations of the of nMOS and pMOS FinFETs are almost the same. From the analytical results, it is found that the variation of the TiN FinFET is due to the work function variation (WFV) of TiN metal gate. The WFV is also responsible for the on-current variation.

An independent-double-gate (IDG) fin-type MOSFET (FinFET) SRAM has been successfully fabricated with considerable leakage current reduction. The new SRAM consists of IDG-FinFETs which have flexible V th controllability. The IDG-FinFET with a TiN metal gate is fabricated by a newly developed gate-separation etching process. By appropriately controlling the V th of the IDG-FinFET, we have successfully demonstrated the reduction of the leakage current and power consumption of the SRAM circuitry.

A compact model (CM) for fin-type FETs (FinFETs) was successfully developed and applied to variability analysis of a fabricated state-of-the-art metal-gate (MG) FinFET. By combining the statistical measurements with the CM calibration, V th variation was, for the first time, broken down into structure-based (silicon fin thickness and gate length) and material-based (gate work function) components. As a result, the measured variation of MG FinFET performance was successfully reproduced by the CM. Characterization using the CM with the measured statistical data provides insight on the gate work function variation of 16 meV in short-channel molybdenum (Mo) gate FinFETs.

Measurement-based analysis of the parasitic resistance (R para) of FinFETs was extended to investigation of R para fluctuation, which could cause severe on-current variation. R para was obtained from the intercept in the linear relationship between measured on-resistance and gate length for FinFETs of various dimensions. A significant increase in R para is observed for fin thickness below 25 nm due to dopant loss from the ultrathin extension during processing. R para variation was evaluated for 45 FinFETs with an average fin thickness of 16 nm. Significant R para variation is observed and correlates with the variation of fin thickness.

A Ta/Mo interdiffusion dual metal gate technology was successfully introduced to FinFET fabrication. The advantage of the proposed technology was examined by using the gate-first process without a metal-etch off step. The Ta/Mo gated nMOS FinFET with a reduced threshold voltage and the Mo gated pMOS FinFET exhibited symmetrical v alues of (0.31/0.36 V), which are desirable for the FinFET CMOS circuit operation with enhanced current drivability. It was also confirmed that the Ta/Mo interdiffusion process causes no degradation in the carrier mobility.

We investigated channel doping in fin-type double-gate (DG) MOSFETs. We demonstrated through experiments that the threshold voltage was more sensitive to the dopants in the accumulation mode than in the inversion mode. We also found that significant deviation in the threshold voltage from the expected value arose in ultrathin fin-type DG MOSFETs. We attributed this phenomenon to the unexpected dopant loss from the ultrathin channels due to segregation. This finding means that careful doping adjustments must be made in ultrathin-channel devices.

Cointegration of titanium nitride (TiN)-gate high-performance tied-gate three-terminal FinFETs with symmetric gate-oxide thicknesses (tox1=tox2=1.7 nm) and variable threshold-voltage Vth independent-gate four-terminal (4T) FinFETs with asymmetric gate-oxide thicknesses (tox1=1.7 nm for the driving-gate-oxide, and tox2=3.4 or 7.0 nm for the control-gate-oxide) has been successfully developed using conventional reactive sputtering, two-step Si-fin and gate-oxide formation, and resist etch-back processes. A significantly improved subthreshold slope and an extremely low OFF-state current Ioff are experimentally confirmed in the asymmetric gate-oxide thickness 4T FinFETs by increasing the control-gate-oxide thickness to twice or more the driving-gate-oxide thickness. The developed techniques are attractive for high-performance and low-power FinFET very large-scale integration circuits

Dynamically power-controllable CMOS inverters have been successfully demonstrated using separated-gate four-terminal (4T) FinFETs. The threshold voltages of the both pMOS and nMOS FinFETs can be flexibly controlled by applying a bias voltage to the control-gate. We demonstrate for the first time that the power consumption of the CMOS inverter can be dynamically controlled using the variable threshold voltage provided by the 4T-FinFET. These results strongly suggest the advantage of the power-managed CMOS circuits using 4T-FinFETs