1. 1000-Pixels Per Inch Transistor Arrays Using Multi-Level Imprint Lithography
- Author
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Auke Jisk Kronemeijer, Lukasz Witczak, Gerwin H. Gelinck, Ilias Katsouras, Joris de Riet, Tamer Dogan, René A. J. Janssen, Thijs Bel, Molecular Materials and Nanosystems, and ICMS Core
- Subjects
010302 applied physics ,Multi-level nanoimprint lithography ,Fabrication ,Materials science ,Industrial Innovation ,Amorphous indium gallium zinc oxide ,business.industry ,Transistor ,Transistor array ,Amorphous Indium Gallium Zinc Oxide thin film transistor ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,law.invention ,Backplane ,law ,Thin-film transistor ,0103 physical sciences ,High-resolution thin film transistor array ,amorphous Indium Gallium Zinc Oxide thin film transistor ,Optoelectronics ,multi-level nanoimprint lithography ,Electrical and Electronic Engineering ,business ,Lithography ,Pixel density - Abstract
Sub-micrometer thin-film transistors (TFTs) are realized using multi-level imprint lithography. Amorphous indium gallium zinc oxide ( $\alpha $ -IGZO) TFTs with channel lengths as small as $0.7~\mu \text{m}$ , field-effect mobility of 10 cm2V−1s−1 and on/off ratio of circa 107 were integrated into a 1000-pixels per inch (ppi) TFT backplane array. The reduction of the number of patterning steps and the inherent self-registration of the most critical transistor layers on top of each other offer a cost-effective high-throughput fabrication route for high-resolution TFT arrays.
- Published
- 2020