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The CMOS silicon avalanche-mode light-emitting diode (AMLED) has emerged as a potential light source for monolithic optical interconnects. Earlier we presented a superjunction light-emitting diode (SJLED) that offers a higher electroluminescent intensity compared to a conventional AMLED because of its more uniform field distribution. However, for reducing power consumption low-voltage (< 15V) SJLEDs are desired, not explored before. In this work we present a TCAD simulation feasibility study of the low-voltage SJLED for various doping concentrations and device dimensions. The results show that for obtaining a constant field, approximately a ten-fold more aggressive charge balance condition in the SJLED is estimated than traditionally reported. This is important for establishing a guideline to realize optimized RESURF and SJLEDs in the ever-shrinking advanced CMOS nodes.

We report on the dependency of the optical power efficiency $\eta $ on the breakdown voltage ${V}_{\text {BR}}$ of avalanche-mode (AM) light-emitting diodes (LEDs) in silicon. Lateral p+-n-n+ LEDs have been designed in a 65-nm bulk CMOS technology, where ${V}_{\text {BR}}$ is varied between 2 and 9 V. This tunes both the magnitude and the spatial distribution of the reverse electric field, which governs AM electroluminescence. Experiments show that a maximum $\eta $ of $\sim 1.7 \times 10^{-6}$ is obtained for ${V}_{\text {BR}} \sim 6$ V. For ${V}_{\text {BR}} V, non-local avalanche results in a lower $\eta $ , while for ${V}_{\text {BR}} > 6$ V, a gradual reduction in $\eta $ with increasing ${V}_{\text {BR}}$ is obtained. This trend is compared with two recently proposed opto-electronic models. A maximum in $\eta $ at relatively low voltages is attractive for monolithic opto-electronic integration in silicon