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We compare the contact characteristics for Mo, Pd, and Ti on n-InGaAs layer with a range of active donor concentration from $1.6 \times 10^{18}$ cm−3 to $4.8 \times 10^{19}$ cm−3. The Fermi level pinning of 0.18 eV lower than the bottom of n-InGaAs conduction band is experimentally manifested. It is also revealed that the contact resistivity ( $\rho _{\text {c}}$ ) of Mo/n-InGaAs contact clearly outperforms after annealing. However, for the first time, we demonstrate that the Mo/Pd (2nm)/n-InGaAs contact can achieve a $\rho _{\text {c}}~35$ % and 20% lower than a single Mo/n-InGaAs contact after annealing at 400 °C and 450 °C for 1min, respectively.

Presence of a native oxide interlayer degrades seriously the contact resistivity ( $\rho _{{\text {c}}}$ ) of co-deposited TiSi (CD-TiSi) on Si:P. The oxide cannot be scavenged by the CD-TSi due to its low solid solubility of O. We tackle the problem by capping the CD-TiSi with an O gettering cap. Utilizing a Ti cap and two-step post-metal rapid thermal anneal, we reduce the $\rho _{{\text {c}}}$ of the CD-TiSi on ${2}\times {10}^{{21}}$ cm $^{-{3}}$ doped Si:P by ${\sim }{3}$ times, down to ${\sim }{2} \times {10}^{-{9}}\,\,\Omega \cdot \text {cm}^{{2}}$ . We also demonstrate efficiency of a La cap to scavenge the oxide.

Non-localized and bipolar switching in vacancy modulated conductive oxide resistive switching devices (TiN/a-Si/TiOx/TiN) is attributed to defect profile modulation in the TiOx switching layer. We observe two modes of operation–stable regular and unstable inverted, corresponding to two sets of opposite switching polarities. This is explained using a kinetic defect distribution model. The position of the defect centroid and the distribution spread determine the switching regime. The unstable inverted regime exposes the reliability concern of erroneous programming which can be avoided by operating in the regular regime with reasonable programming margin.

In this letter, the contact properties and thermal stability of TiN/Ti/p+ -Si0.3Ge0.7 contacts are investigated. We demonstrate that the insertion of an ultra-thin Ti interlayer is necessary to reduce the contact resistivity ( $\rho _{c}$ ) as compared with a standard TiN/p+-Si0.3Ge0.7 direct contact. However, the Ti interlayer has to be thin enough to avoid degradation of the contact morphology after 500 °C annealing. This letter reveals further that the Ti encroachment into grooved SiGe regions under the contact interface is responsible for the $\rho _{c}$ increase seen after this annealing.

In this letter, we investigate contacts of a low work function rare-earth metal, La, and its silicides on n-Si. LaSi x / ${n}^{-}$ -Si contacts show low Schottky barrier height ( $\varphi _{b}$ ) of around 0.25–0.4 eV and promisingly low contact resistivity ( $\rho _{c}$ ) on moderately doped ${n}^{+}$ -Si. However, on highly doped ${n}^{++}$ -Si, we find $\rho _{c}$ of LaSi x near one order higher than the TiSi x control. This experiment indicates that low $\varphi _{b}$ does not guarantee low $\rho _{c}$ on highly doped substrates. We further discuss reasons behind this phenomenon.

This letter proposes a metric to assess the quality of high-k dielectrics on III–V substrates and a benchmarking methodology for the gate stack qualification in the region of MOS device operation above threshold voltage, ${V}_{t}$ . The metric is based on a capacitive equivalent thickness (CET) - normalized frequency dispersion ( $\text{D}_{\mathrm {eff}}$ ) evaluated in the accumulation region of capacitance–voltage (C–V) measurements of III–V MOS devices. ${D} _{\mathrm {eff}}$ is found to be CET independent, which allows for a preliminary assessment of the dielectric quality by using relatively thick layers. Several gate stacks, single layer or bi-layer, including those with Al2O3, and the recently reported ASM-imec interfacial layer (IL) with HfO2 are evaluated and compared against Si MOS devices. Using the proposed technique, a clear difference between the various deposition processes is observed. The results indicate that the quality of a single layer Al2O3 or a bi-layer stack of Al2O3/HfO2 on InGaAs is significantly lower compared with Si gate stacks while the ASM-imec IL yields a gate-stack with good performance on the proposed quality metric. In addition, these results correlate well with the reliability performance of the studied gate stacks.

© 2016 IEEE. Ti/p-Ge and NiGe/p-Ge contacts are compared on both planar- and fin-based devices. Ti/p-Ge contacts show low contact resistance, while NiGe/p-Ge devices show short circuit problems due to thermally driven Ni diffusion. Considering the thermal budget in the standard backend of line processing for CMOS, Ti is more suitable for p-Ge devices. A low Ti/p-Ge contact resistivity of 1.1 × 10-8 Ω cm2 is achieved by using a multi-pulse laser annealing technique for B activation. ispartof: IEEE Electron Device Letters vol:37 issue:4 pages:482-485 status: published

The metal resistance in the transmission line model (TLM) structures creates a serious obstacle to determine precisely the intrinsic contact resistivity. To tackle this problem, we propose a new model, the Lump Model, to evaluate the metal resistance influence in both TLM and circular TLM (CTLM) test structures. In this work, we demonstrate the high simplicity, great robustness and flexibility of the Lump Model. The previous reported contact resistivity values extracted with CTLM are usually above 1×10-7 Ω·cm2 because the metal resistance impact is commonly neglected. This is the first time that the role of the metal in CTLM is appropriately analyzed. Low contact resistivity, 3.6×10-8 Ω·cm2, of standard NiSi/n-Si contact has been extracted and this shows the high sensitivity of this method. ispartof: IEEE Electron Device Letters vol:35 issue:9 pages:957-959 status: published

This letter reports that the effective work function (eWF) of Ni-Fully Silicided (Ni-FUSI) devices with HfSiON gate dielectrics can be modulated toward the silicon conduction band-edge by deposition of an ultra-thin Dy2O3 cap layer on the host dielectric. The obtained eWF depends on the deposited cap layer thickness and the Ni-FUSI phase, with 10 Aring Dy2O3 cap resulting in DeltaeWF ap 400 meV and final eWF ap 4.08 eV for NiSi-FUSI. Dielectric intermixing occurs without impacting the VT uniformity, gate leakage, mobility, and reliability. Well-behaved short-channel devices ( Lg ~ 100 nm, SS ~ 70 mV/dec, and DIBL ~ 65 mV/V) are demonstrated for both HfSiON and [HfSiON/Dy2O3 cap (5 Aring)] devices with NiSi-FUSI gates, corresponding to a similar . This capping approach, when combined with Ni-silicide FUSI phase engineering, allows (n-p) values up to 800 meV, making it promising for low- CMOS.

This paper investigates the extraction of channel length from split current-voltage (C-V) measurements of small gate length PMOS transistors. Using device simulations, including quantum-mechanical effects, scanning spreading resistance measurements, and process simulations, the authors correlate the variation of the overlap capacitance with the gate voltage, and the length of the lateral junction doping profile. It is suggested that an accurate extraction of the metallurgical and effective gate length can be obtained from C-V measurements subtracting the overlap capacitance at V/sub G/=V/sub FB/ and V/sub G/=V/sub FB/+0.8V.

Trap spectroscopy by charge injection and sensing method was applied to the In0.53Ga0.47As-Al2O3 system, yielding the spatial and energetic distribution of the traps inside the Al2O3 layer. The trap density inside the atomic-layer-deposited (ALD) Al2O3 layer was found to be significantly reduced by (NH4)2S treatment of the InGaAs surface prior to the Al2O3 deposition. Indium concentration inside the Al2O3 layer was found to be reduced once the InGaAs surface is (NH4)2S treated prior to the Al2O3 deposition as measured by time-of-flight secondary ion mass spectroscopy, indicating indium as a possible origin of the oxide traps. The results suggest a new mechanism for the sulfur action at the InGaAs surface, which might be responsible for the transistor performance improvements observed after ( NH4)2S passivation. This mechanism involves sulfur as an indium diffusion/segregation barrier stabilizing the InGaAs surface during the ALD Al2O3 deposition, lowering the oxide trap density. This, in turn, improves the electron mobility through a reduction in the Coulomb scattering of the carriers due to border traps and improves the device drive current.

An integrated poly-SiGe-based piezoresistive pressure sensor, which is directly fabricated above 0.13 m Cu-back-end CMOS technology, is presented. This represents not only the first integrated poly-SiGe pressure sensor directly fabricated above its readout circuit but also the first time that a poly-SiGe MEMS device is processed on top of Cu-back-end CMOS. Despite the low processing temperature (455°C) to allow for above-CMOS integration, the poly-SiGe piezoresistive sensor alone (250 250 m2 membrane) showed a sensitivity of around 2.5 mV/V/bar. The same sensor exhibited a sensitivity of 159.5 mV/V/bar after on-chip amplification. The CMOS circuit showed no significant deterioration after the MEMS processing, although a resistance increase for the Cu-filled metal-to-metal and the tungsten-filled CMOS-MEMS vias was observed.

Through-silicon via (TSV) constitutes a key component interconnecting adjacent dies vertically to form 3-D integrated circuits. In this letter, we propose a method to exploit the TSV C-V behavior in a p-silicon substrate to achieve minimum TSV capacitance during 3-D circuit operation. The nature of the TSV C-V characteristics depends both on TSV architecture and TSV manufacturing process, and both these factors should be optimized to obtain the minimum depletion capacitance in the desired operating voltage region. Measured C-V characteristics of the TSV demonstrate the effectiveness of the method.

In Germanium-based metal-oxide-semiconductor field-effect transistors, a high-quality interfacial layer prior to high-? deposition is required to achieve low interface state densities and prevent Fermi level pinning. In this letter, the physical and electrical properties of a Ge/GeO2/Al2O3 gate stack are investigated. The GeO2 interlayer grown by radical oxidation and the formation of a germanate (GeAlOX) layer at the interface provide a stable high-quality passivation of the Ge channel. High carrier mobilities (235 cm2/V·s for electrons and 265 cm2/V·s for holes) are demonstrated for a relatively low 3.7-nm equivalent oxide thickness (EOT), enabling the realization of a high-performance CMOS technology with potential EOT scaling.

We applied the developed trap spectroscopy by charge injection and sensing to validate the extraction of the silicon nitride trap distribution (both in space and energy) from the modeling of retention transients of charge-trapping memories. We compared three different types of silicon nitrides using these two techniques, and similar distributions were extracted, thus confirming the validity of the charge profiles resulting from the modeling of retention transients and the physics of the proposed model, based on two main mechanisms of charge loss: Poole-Frenkel emission (dominating at high temperature) and direct tunneling (dominating at room temperature).

The shift-and-ratio method has been considered as one of the most accurate and consistent techniques for extracting the effective channel-length of the MOS transistor. This method assumes the effective mobility of a long channel and a short channel transistor to be equal. Scaling down the MOS transistor urges the need of including halo (or pocket) implants in the fabrication process. Due to this implant, however, the short channel MOSFET features a degraded effective mobility compared to the long channel reference device. This affects the channel-length extraction and results in unrealistic high values for the extracted effective channel-length for deep submicron transistors with high-dose halo (or pocket) implants.

Ge pMOSFETs with gate lengths down to 70 nm are fabricated in a Si-like process flow. Reducing the LDD junction depth from 24 to 21 nm effectively reduces short-channel effects. In addition, a reduced source/drain series resistance is obtained using pure boron LDD implants over BF2, resulting in a significant I ON boost. Benchmarking shows the potential of Ge to outperform (strained) Si, well into the sub-100-nm regime. The 70-nm devices outperform the ITRS requirements for I ON by 50%, maintaining similar I OFF, as measured at the source.

The impact of aluminum (Al) implantation into TiN/SiO2 on the effective work function (EWF) of poly-Si/ TiN/SiO2 is investigated. Al implanted at 5 keV with a dose of 5 times 1015 cm-2 reduces the flatband voltage (VFB) and the EWF of poly-Si/TiN/SiO2 stack by ~150 mV compared with the unimplanted poly-Si/TiN/SiO2 stack. This reduction of VFB is found to be dose-dependent, which is correlated to the Al concentration at the TiN-SiO2 interface as evidenced by secondary-ion-mass-spectrometry profiles. The interface dipole created due to the Al presence at the metal-dielectric interface is believed to contribute to the observed VFB (or EWF) reduction (or increase). This technique for EWF modulation is promising for further threshold-voltage (Vt) tuning without any process complexities and is quite significant for planar and multiple gate field-effect transistors on fully depleted silicon on insulator.

In this letter, we report that by using a thin dysprosium oxide (Dy2O3)cap layer (~1-nm thick) on top of SiON host dielectrics, the threshold voltage (Vt) of poly-Si/TaN gated n-FETs can be modulated to match that of the reference poly-Si/SiON devices, with a significantly scaled equivalent oxide thickness, a much reduced gate leakage, improved time-zero-break-down characteristics, and a minor degradation of the long channel devices mobility. These effects are attributed to the formation of a DySiON layer formation after full device fabrication due to the intermixing between the Dy2O3 cap and the SiON layer, as evidenced by a cross-sectional transmission-electron-microscopy measurement.

A new operating mode for the nitride-based nonvolatile memory cells using channel hot electron injection for programming and hot hole injection for erasing is presented. The mismatch between the injected electron and hole profiles during programming and erasing operations, which limits the performance of the device, can be prevented. The profiles, extracted from charge-pumping measurements, are tuned by changing the operating voltages in order to have matched distributions. Substantial improvements in endurance and subsequent high-temperature data retention are demonstrated

Recessed Si/sub 0.8/Ge/sub 0.2/ source/drain (S/D) and a compressive contact etch-stop layer have been successfully integrated resulting in nearly 200% improvement in hole mobility. This is the largest reported process-induced hole mobility enhancement to the authors' knowledge. This letter demonstrates that a drive-current improvement from recessed Si/sub 0.8/Ge/sub 0.2/ plus the compressive nitride layer are in fact additive. Furthermore, it shows that the mobility enhancement is a superlinear function of stress, leading to larger than additive gains in the drive current when combining several stress sources.

The low-frequency noise behavior of locally strained pMOSFETs with a 7HfO/sub 2//TiN gate stack is reported. Different ways of compressive-strain engineering have been compared: a Si/sub 3/N/sub 4/ cap layer, SiGe source/drain (S/D) regions, or the combination of both. It is shown that the use of a cap layer does not degrade the 1/f noise magnitude, while an increase of this parameter is found for SiGe S/D devices. This increase is ascribed to the creation of additional traps in the high-k oxide by the SiGe S/D processing. The effect appears to be independent of the germanium content in the range studied (15%-25%). Another conclusion is that no direct correlation has been observed here between the applied stress and the noise magnitude.

The impact of TiN film thickness variations on the effective work function (WF) of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON interfaces has been investigated. The electrical signatures of these gate stacks indicate that the concentration of Hf-Ti and Ti-Si bonds at the (poly-Si/TiN)/HfSiON and (poly-Si/TiN)/SiO/sub 2/ interface plays a significant role on the control of the gate stacks' WF. The density of these interfacial bonds and the related work function changes are correlated to the degree of nucleation of the TiN film on the dielectric.

In this letter, we investigate the influence of tensile and compressive SiN layers on the device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 nm. It will be shown that even for narrow fin devices, the nMOS performance improvement can be as high as 20% with tensile strained layers. The improvement seen for pMOS is lower, about 10%. Next to that both compressive as well as tensile SiN layers can increase the pMOS on-state current.

Hole mobility is found to more than double in fabricated p-MOSFETs with SiGe source/drain due to longitudinal compressive stress in the channel exceeding 1 GPa. The maximum observed low-field mobility enhancement is 140% at a simulated stress level of 1.45 GPa. The mobility enhancement is approximately linear with stress at moderate levels but becomes super-linear above 1 GPa. An important consequence of this behavior is that for moderate stress levels, an average channel stress can be used to estimate the performance of transistors with a nonuniform stress distribution across the channel width. Two alternative approaches to model stress-enhanced hole mobility are suggested. Analysis of the physical effects behind the experimental observations reveals the relative roles of band repopulation and mass modulation. In addition, previously published wafer bending experiments with compressive stress levels below 400 MPa are used to implicitly verify the accuracy of the stress simulations.

In this letter, we have fabricated a functional FinFET ring oscillator with a physical gate length of 25 nm and a fin width of 10 nm, the smallest ever reported. We demonstrate that these narrow (W/sub fin/ = 10 nm) and tall (H/sub fin/ = 60 - 80 nm) fins can be reliably etched with controlled profiles and that they are required to keep the short-channel effects under control, resulting in drain-induced barrier leakage characteristics of 45 mV/V at V/sub dd/ = 1 V and L/sub g/ = 25 nm for the nFET. For these ultrathin (10 nm) fins, we have succeeded in properly setting the V/sub T/ at 0.2 V without the use of metal gates. In addition to ring oscillators, we also have obtained excellent pFET FinFET devices at wider fin widths (W/sub fin/ = 65 nm) with I/sub dsat/ = 380 /spl mu/A//spl mu/m at I/sub off/ = 60 nA//spl mu/m and V/sub dd/ = -1.2 V.

Low-voltage low-power nonvolatile floating-gate memory device operation can be achieved by using alternative tunnel barriers consisting of at least two dielectric layers with different dielectric constants k. Low-k/high-k (asymmetric) and low-k/high-k/low-k (symmetric) barriers enable steeper tunneling current-voltage characteristics. Their implementation is possible with high-k dielectric materials that are currently investigated for SiO/sub 2/ replacement in sub-100-nm CMOS technologies. We show that a reduction in programming voltages of up to 50% can be achieved. This would significantly reduce the circuitry required to generate the high voltages on a nonvolatile memory chip, while maintaining sufficient performance and reliability.

In this work, we introduce the Spacer/Replacer concept, a new concept to improve the device performance of ultrathin-film fully-depleted (FD) SOI CMOS transistors. High-performance FD SOI CMOS transistors are demonstrated with a silicon film thickness of 30 nm and physical gate-lengths down to 0.1 /spl mu/m. The approach uses selective epitaxial growth of silicon to form raised source/drains while avoiding the simultaneous formation of a T-shaped poly-Si gate. In addition, the introduced concept eases the integration issues related to the ultrathin silicon film.

A semianalytical model of the through-silicon via (TSV) capacitance for elevated operating temperatures is derived and verified with electrical measurements. The effect of temperature on the increase in TSV capacitance over different technology parameters is explored, and it is shown that higher oxide thickness reduces the impact of temperature rise on TSV capacitance, while with low doped substrates, which are instrumental for reducing the TSV capacitance, the sensitivity of TSV capacitance to temperature is large and cannot be ignored.

The source and drain (S/D) structure is a key element in scaling down the MOSFET for low-power applications below 0.25-/spl mu/m dimensions. Here, we report on a simple test structure and show how more detailed information on the parasitic series resistance components of deep submicron devices can be obtained. Specifically, the dependence of the different resistance components on the process parameters like dose and energy of implantation, temperature treatment, spacer width, and silicide formation can be investigated with high accuracy.