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To promote the practical application of ferroelectric devices, we present a systematical study on ferroelectric properties of 10nm HZO capacitor at the high temperature application scenarios (300K-400K). We found that the Pr value decreases with the increase of temperature (thermal induced Pr degradation, TIPD) and this phenomenon mainly occurs in the case of low electric field operation. By using in-situ material characterization, it is proved that this phenomenon is not caused by phase transition. Further research on trap generation and redistribution through electrical characterization reveals that TIPD is related to the internal electric field ( $\text{E}_{\text {bias}}{)}$ caused by charge de-trapping. The deep insight into the underlying mechanism of TIPD provides a useful perception for advancing the practical application of ferroelectric devices.

In this letter, HfO2-based junctionless ferroelectric-gate field effect transistors (FeFETs) and the FeFET NAND memory arrays are proposed and experimentally demonstrated, on FDSOI. High performance including ultra-low leakage( $\sim $ pA) and ultra-high $\text{I}_{\text {PGM}}/\text{I}_{\text {ERS}}$ ratios ( $10^{{5}}{)}$ can be achieved. Furthermore, the memory functions of the NAND arrays are experimentally demonstrated. FDSOI-based NAND FeFETs will be promising for the next-generation high density, low power memory and edge computing.

The back-end-of-line (BEOL) process compatibility is one of the advantages of Hf0.5Zr0.5O2 (HZO)-based ferroelectric (FE) among other kinds of HfO2-doped FEs. However, the impact of stress effect induced by the interconnects during device stacking cannot be ignored. Previous studies about the stress effect have mainly focused on the metal in direct contact with the FE layer, but have neglected the potential effects of other layers covering the electrodes. In this work, the stress effects of interconnecting metals including Cu and W, which are the most mainstream interconnects in modern integrated circuit (IC) technology, are systematically demonstrated. The capping layers can exert stress on the top electrode (TE), and this stress transfers to the HZO layer during annealing, which affects the crystalline state of HZO films and enhances or suppresses the ferroelectricity. This is verified by the devices’ electrical performance, the residual stresses measurements and grazing-angle incidence X-ray diffraction results. The results can guide the selection of the proper annealing timing for large-scale FE memory integration when utilizing the BEOL process with different interconnects.

High-performance ferroelectric devices compatible with the Back-End-of-Line (BEOL) process are necessary for their mass production and application. In this letter, pre-crystallization engineering of increasing the number of cycles of ZrO2 and HfO2 in each period of Hf $_{{0.5}}$ Zr0.5O2 (HZO) film growth process was utilized to improve the ferroelectric property of TiN/HZO/TiN capacitors at 400°C annealing process. Grazing incidence X-ray diffraction shows that higher in-situ crystallized tetragonal phase nuclei can be formed in the HZO film with 3 cycles of ZrO2 and 3 cycles of HfO2 (3Z3H) in each period during the ALD step at 280°C, which will enhance the formation of ferroelectric orthorhombic phase after rapid thermal annealing. The developed TiN/3Z3H/TiN capacitor shows high remnant polarization ( $2{P}_{r}$ ) of $45 ~\mu \text{C}$ /cm2, and better endurance of more than $10^{{10}}$ cycles.