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Voltage-induced recovery of dielectric breakdown is a well known phenomenon that has recently been proposed as an effective technique to rejuvenate nanoscale device performance and enhance the reliability lifetime of ultrathin high-\kappa gate stacks. Considering that most of the circuits at operating conditions take years to suffer soft breakdown (BD) as estimated by extrapolation models, it would be potentially useful to probe whether the pre-BD defect generation-induced time-dependent leakage evolution of the dielectric, commonly referred to as the stress-induced leakage current (SILC), can be reversed permanently so that circuit performance is enhanced from time to time even before the percolation event. In this letter, we investigate the feasibility of SILC recovery in state-of-the-art sub-10-Å equivalent oxide thickness TiN\--TaN\--HfLaO\--SiOx gate stacks by arresting the degradation of the dielectric using carefully chosen compliance values representative of the pre-BD regime. Our results clearly show the improvement in the saturation drive current and transfer characteristics and reduction in gate leakage and noise spectrum in the SILC stage by initiating a simple negative polarity sweep. Reversibility of SILC is attributed to the backward drift of mobile oxygen ions stored in the oxygen soluble metal gate. [ABSTRACT FROM PUBLISHER]

We study the mechanism of filamentation in resistive switching (RS) memory from an electrical perspective using a conventional metal–insulator–semiconductor (MIS) high- \kappa metal gate transistor test structure and propose the possibility of using the same transistor structure for both logic and RS memory applications. The filament location is measured after every SET transition, and our investigations point to a “pseudorandom” nature of filament nucleation. Migration of highly diffusive nickel from source/drain silicide contacts toward the active silicon channel region transforms the existing MIS stack to MIM, thereby enabling the RS phenomenon. [ABSTRACT FROM AUTHOR]

We propose the use of high-oxygen-solubility metalgate electrodes as a material of choice for high- \kappa gate stacks in order to prolong the time-dependent-dielectric-breakdown (BD) reliability. Our findings on n-channel metal–oxide–semiconductor devices with these gate electrodes reveal that the application of low negative bias stress after a soft-BD (SBD) event helps to restore the oxygen ions and passivate the oxygen vacancy traps that comprise the percolation path. This can be a simple yet effective designfor-reliability tool to initiate the self-repair of the percolation path and operate the circuit for a prolonged period after repair. The only requirement for achieving this SBD reversibility is to choose gate electrodes that can serve as good oxygen reservoirs. [ABSTRACT FROM PUBLISHER]

We modify the existing oxide breakdown (BD) percolation model in this letter to account for the presence of microstructural weakest link grain boundary (GB) defects in polycrystalline high-\kappa (HK) gate stacks. The different rates of the stress-induced leakage current degradation and oxide trap generation at the bulk and GB regions need to be accounted for in modeling the statistical nature of BD in HK dielectric thin films. Simulated results reveal the dominance of GB-related failures and the origin of the non-Weibull stochastics inherent in polycrystalline HK stacks. We also point to the inability of conventional percolation models with an assumed uniform defect generation to describe the failure statistics of current HK gate stacks. [ABSTRACT FROM AUTHOR]

We report the use of 1/fα noise spectrum in the postbreakdown regime, extracted from random-telegraph-noise signals of gate current at low sense voltages, as a characterization tool to detect the layer which breaks down first in dual-layer high-κ (HK) and interfacial-SiOx-layer (IL) dielectric stacks. The power law exponent (α) of the low-frequency power-spectral-density plot and the time constant of the discrete current fluctuations reveal that the HK is almost always the first layer to break down for positive gate-stress conditions in NMOS devices. From a reliability point of view, the presence of the IL layer helps to prolong the lifetime of HK gate stacks, which may suffer from time-dependent dielectric breakdown. [ABSTRACT FROM AUTHOR]