Search

Recent development on 3D flash memories largely promotes the wide application of Solid-State Drives (SSDs) by providing larger capacity from vertically-stacked layers. However, there exist speed variations across different layers because of manufacturing process variations or physical designs, which induces new challenges to fully explore the advantages of existing SSDs, e.g. the parallel structure. This paper investigates the effect of speed variation on the parallel performance of SSDs. To balance chips’ workloads, traditional method selects chips in a round-robin way. As chip queue time can be estimated by some main factors, the chip also can be chosen in a greedy way. However, because of the layer speed variation, queue time estimation model should be modified. This paper first establishes a new queue time estimation model with the awareness of the flash layer information. Then the model is used to estimate the chip queue time and to direct write requests into the chip with the least queue time. The key idea is to largely reduce queue time of each write, thus reducing the average SSD response time. Finally, this new request redirection method is evaluated on SSDsim with real world workloads. Experimental results show that our model can estimate the queue time more accurately and our new request redirection method can improve 8.3% of write queue time on average under the situation of 4 times speed variation among 16 layers.

Address space layout randomization (ASLR) is now widely adopted in modern operating systems to thwart code reuse attacks. However, an adversary can still bypass fine-grained ASLR by exploiting memory corruption vulnerabilities and performing memory disclosure attacks. Although Execute-no-Read schemes have been proven to be an efficient solution against read-based memory disclosures, existing solutions need modifications to kernel or hypervisor. Besides, the defense of execution-based memory disclosures has been ignored. In this paper, we propose BoundShield, a self-protection scheme that provides comprehensive protection against memory disclosure attacks, especially against those based on executing arbitrary code by leveraging Intel Memory Protection Extension . BoundShield protects code memory by defending not only read-based memory disclosure attacks but also execution-based memory disclosure attacks. On one hand, read-based memory disclosures can be eliminated by hiding all code sections and code pointers in a secret region separated from the user address space. On the other hand, BoundShield prevents return addresses from being corrupted and ensures that all function pointers point to the legitimate entries whenever they are dereferenced, which significantly reduces the attack surface for execution-based memory disclosures. We have implemented a prototype of BoundShield based on a set of modifications to compiler toolchain and the standard C library. Our evaluation results show that the BoundShield can provide strong defenses against memory disclosure attacks while incurring a small performance overhead.

3D-multi-level cell (MLC) NAND flash memory adopts 3D stack technology and stores two bits per cell, leading to improved storage capacities, but sacrificing data reliability. Low-density parity-check (LDPC) codes showing strong error correction capability benefit from their soft decision decoding, which is widely exploited to guarantee data reliability. Nevertheless, adopting LDPC codes can introduce a concern about read performance, because their iterative soft-decision decoding requires Log-Likelihood Ratio (LLR) information, called soft decision information, by applying multi-sensing voltages. This process of obtaining LLR information leads to high sensing and transferring latencies, lowering down 3D-MLC read performance. In particular, when raw bit error rates (RBER) are much higher due to the long retention periods and program/erase (P/E) cycles, this problem becomes more serious. In this paper, we propose a RBER-aware multi-sensing scheme for reducing sensing and transferring latencies, and thus improving read performance. This proposed scheme exploits the variations of RBER in flash pages with the increase of retention time and P/E cycles to dynamically apply sensing voltages. Simulation results show that this scheme significantly decreases the number of required sensing voltages while maintaining LDPC error correction capability, enhancing 3D-MLC read performance.