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Due to the ongoing slowdown of Dennard scaling, heterogeneous hardware architectures are inevitable to meet the increasing demand for energy efficient systems. However, one of the most important aspects that shape today’s computing landscape is the wide availability of software that can run on any system. Current applications that use accelerators, in contrast, are often especially tailored to a specific hardware setup and therefore not universally deployable. This is particularly true for reconfigurable logic as their internal structure requires the circuits and their integration to be designed as well. This makes them inherently difficult to use and therefore less accessible for a general audience. Nevertheless, their balance of flexibility and efficiency puts reconfigurable accelerators in a unique position between CPUs, GPUs, and ASICs. Therefore, one of the main challenges of future heterogeneous systems is to foster collaborative computing between these vastly different components while still being simple to use. Previous approaches mostly focused on subproblems instead of a holistic view of hardware and software in the context of commonplace usability. This paper analyzes the general demands on a reconfigurable platform and derives their requirements regarding accessibility and security. Hereby, we investigate several key features like hardware virtualization, system shared virtual memory, and the use of wide-spread programming paradigms. Then, we systematically build up such a platform based on the established ROCm GPU framework and its internal HSA standard. This new common HERA methodology is finally also demonstrated as a prototype.

In the era of IoT, embedded systems are becoming the cornerstone of many IoT related applications, such as smart cars and wearable devices. However, embedded devices have numerous constraints and requirements, including stringent area and power, reduced cost and time-to-market, and increased speedup. Furthermore, these applications are becoming increasingly compute/data-intensive requiring more processing power. Also, especially for IoT related applications, security is another major issue in resource-constrained embedded devices. Although cryptographic algorithms are widely used to ensure the security of these applications, commonly used ones, such as AES, are unsuitable for highly constrained embedded devices, due to their sheer complexity. Hence, several lightweight cryptographic algorithms were proposed in the literature that might be better suited for embedded devices. From these, SPECK and SIMON, introduced by NSA, are the two most popular ones. Another important challenge is how to incorporate the cryptographic algorithms in to embedded devices, efficiently and effectively, without compromising the integrity of the compute/data-intensive applications running on these small-footprint devices. Our previous analysis demonstrated that FPGAs are currently the best avenue to support compute/data-intensive applications running on resource-constrained embedded devices, due to FPGA's many attractive traits, including, post-fabrication reprogrammability, dynamic and partial reconfiguration capabilities, and reduced time-to-market. Also, FPGAs can be utilized to provide several advantages/features required for the embedded device's security, such as cryptographic algorithm agility, algorithm upload, algorithm modification, and resource efficiency. In this research work, we introduce novel, unique, and efficient dynamic and partial reconfigurable hardware architectures for the most popular SPECK and SIMON algorithms on embedded devices, considering the constraints associated with these devices and the requirements of the applications running on embedded devices. We also introduce unique system-level architectures for our proposed designs. To the best of our knowledge, no similar work exists in the literature that provides dynamic and partial reconfigurable hardware for SPECK and SIMON, and also provides system-level architecture. Our dynamic and partial reconfigurable hardware designs achieve 28% space saving compared to its static reconfigurable hardware, and 59 times speedup compared to its software counterpart.

With advancements in compute-intensive and memory-bound applications, the need for faster and more energy-efficient processing platforms continues. In support of these advancements, heterogeneous platforms have been proposed to enhance the performance and efficiency in the cloud. These platforms include field programmable gate arrays and graphical processing units in addition to general-purpose processors. Furthermore, there is a strong interest in advancing active solid-state drives to support both storage and computation. In this paper, we present a generic formulation to support the modeling of such a heterogeneous cloud environment, without being specific to a particular cloud platform such as Spark or Hadoop. We represent the cloud as a collection of clients, middleware control nodes, and high performance compute nodes (HPN), where the HPNs represent the options of advanced compute technologies in a heterogeneous cloud. The objective of the paper is to present a simple and efficient formulation for scheduling applications in such a heterogeneous cloud. Consistent with recent software modeling of artificial intelligence applications, we propose to map applications into directed acyclic graph representations of tasks. The optimization problem is then formulated to infer the best scheduling of tasks on the HPNs, while minimizing the overall execution time and data communication delays between nodes. Unlike existing scheduling algorithms that assume equal performance across nodes, our formulation explicitly takes into account the different compute capabilities of the heterogeneous nodes. The resulting task scheduling is then evaluated to provide insights into the performance gains with the proposed advanced heterogeneous cloud computing environment. The results show improved performance when comparing the proposed taskscheduling algorithm with the genetic algorithm and heterogeneous earliest finish time algorithms. We also show the performance gains achieved with the optimal task scheduling on a heterogeneous cloud system as compared with a conventional CPU-only cloud system.

The main purpose of this paper is to investigate the feasibility of using field programmable gate arrays (FPGAs) chips as alternatives for the conventional CPUs to accelerate the numerical solution of the fluid dynamics differential equations. FPGA is an integrated circuit that contains an array of logic blocks, and its architecture can be reprogrammed and reconfigured after manufacturing. Complex circuits for various applications can be designed and implemented using FPGA hardware. The reconfigurable hardware used in this paper is a system on a chip FPGA type that integrates both microprocessor and FPGA architectures into a single device. In this paper, typical computational fluid dynamics problems, such as the Laplace and 1-D Euler equations, are implemented and solved numerically on both reconfigurable hardware and CPU. The precision of results and speedups of the calculations is compared together. In some cases, the computational process on FPGA is up to 20 times faster than a conventional CPU, with the same data precision. Several numerical and analytical solutions are used to validate the results.