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The ferroelectric field-effect transistor (FeFET) is one of the most promising candidates for emerging nonvolatile memory devices owing to its low write energy and high $I_{\mathrm {ON}}/I_{\mathrm {OFF}}$ ratio. For FeFET applications as nonvolatile memory devices, 1FeFET, 1T-1FeFET, 2T-1FeFET, and 3T-1FeFET cells have been proposed. The 1FeFET cell exhibits the highest density but suffers from write disturbance. Although the 1T-1FeFET and 2T-1FeFET cells resolve the write disturbance, they use a write scheme with a negative write voltage ( $V_{\mathrm {W}}$ ), which requires voltage swings of many control signals, leading to a significantly high write energy consumption. The 3T-1FeFET cell uses a write scheme without a negative $V_{\mathrm {W}}$ ; however, it exhibits the largest area overhead. Although the 1T-1FeFET cell resolves the write disturbance with a small area overhead; however, it exhibits high write energy consumption because of the use of a negative $V_{\mathrm {W}}$ . In this paper, to significantly reduce the write energy consumption, we propose a less control signal swing (LCSS) write scheme without using a negative $V_{\mathrm {W}}$ . Simulation results indicate that the worst, average, and best cases of the proposed LCSS write scheme can achieve 35%, 66%, and 96% lower write energy consumption, respectively, than the write scheme with a negative $V_{\mathrm {W}}$ in the 1T-1FeFET cell. We also identify the available sensing schemes for each FeFET cell in the read operation according to the FeFET threshold voltage distribution.

Recently, nonvolatile systems with nonvolatile flip-flops (NVFFs) have gained prominence for their energy efficiency in energy-harvesting devices and battery-operated Internet of Things applications. They are normally-off instantly-on, and thus, can save energy effectively owing to their zero standby power consumption. An NVFF stores the computing state in nonvolatile memories (NVMs) when the power is off. A ferroelectric field-effect transistor (FeFET) is one of the most promising NVMs owing to its high $\text{I}_{\mathrm {on}}/\text{I}_{\mathrm {off}}$ ratio and low write power. Three FeFET-based NVFFs (previous FeFET-out NVFF-1/-2 and FeFET-in NVFF) were recently proposed to improve the area, power, and speed; however, they still have their own problems. Previous FeFET-out NVFF-1 has large area overhead and previous FeFET-out NVFF-2 does not properly perform restore operation. Previous FeFET-in NVFF has a long clock-to-Q delay and high operating energy. This paper introduces two novel FeFET-based NVFFs (proposed FeFET-out and -in NVFFs). Proposed FeFET-out NVFF reduces the large area overhead of previous FeFET-out NVFF-1 and corrects the malfunction in the restore operation of previous FeFET-out NVFF-2. Proposed FeFET-in NVFF achieves a better clock-to-Q delay, operating energy, and area than the previous FeFET-in NVFF. Monte Carlo simulations based on an industry-compatible 10-nm FinFET model are performed for a comparative analysis. Proposed FeFET-out NVFF achieves 17.6% smaller area with slightly higher (6.3%) operating energy and only 0.8% slower clock-to-Q delay than previous FeFET-out NVFF-1. Proposed FeFET-in NVFF achieves 18.9% shorter clock-to-Q and 3.0% smaller operating energy with 8.7% smaller area than the previous FeFET-in NVFF.