Search

Orbital angular momentum-shift keying (OAM-SK), which is the rapid switching of OAM modes, is vital but seriously impeded by the deficiency of OAM demodulation techniques, particularly when videos are transmitted over the system. Thus, in this paper, 3D chaotic interleaved multi-coded video frames (VFs) are conveyed via an N-OAM-SK free-space optical (FSO) communication system to enhance the reliability and efficiency of video communication. To tackle the defects of the OAM-SK-FSO mechanism, two efficient deep learning (DL) techniques, namely convolution recurrent neural network (CRNN) and 3D convolution neural network (3DCNN) are used to decode OAM modes with a low bit error rate (BER). Moreover, a graphics processing unit (GPU) is used to accelerate the training process with slight power consumption. The utilized datasets for OAM states are generated by applying different scenarios using a trial-and-error method. The simulation results imply that LDPC-coded VFs achieve the largest peak signal-to-noise ratios (PSNRs) and the lowest BERs using the 16-OAM-SK model. Both 3DCNN and CRNN techniques have nearly the same performance, but this performance deteriorates in the case of larger dataset classes. Moreover, the GPU accelerates the performance by almost 67.6% and 36.9% for the CRNN and 3DCNN techniques, respectively. These two DL techniques are more effective in evaluating the classification accuracy than the other traditional techniques by almost 10 – 20%.

A digitized analog signal often encounters a high-frequency noisy background which degrades the signal-to-noise ratio (SNR) particularly in case of low signal strength. Despite quite a lot of hardware- and software-based approaches have been reported to date to deal with the noise issue, it is still a challenging task to real-time retrieve the noise-contaminated low-frequency information efficiently without degrading the original bandwidth. In this paper, we report a modified unsharp-masking (UM)-based Graphics Processing Unit (GPU)-accelerated algorithm to efficiently suppress a high-frequency noisy background in a digitized two-dimensional image. The proposed idea works effectively even if noise-density is high and signal of interest is comparable or weaker than the maximum noise level. While suppressing the noisy background, the original resolution remains least compromised. We first explore the effectiveness of the algorithm by means of simulated images and subsequently extend our demonstration towards a real-world life-science imaging application. Securing a potential for real-time applicability, we implement the algorithm via Compute Unified Device Architecture (CUDA)-acceleration and preserve a $ < 300~\mu \text{s}$ processing time for a $1000\times 1000$ -sized 8-bit data set.

Sample entropy is a widely used method for assessing the irregularity of physiological signals, but it has a high computational complexity, which prevents its application for time-sensitive scenes. To improve the computational performance of sample entropy analysis for the continuous monitoring of clinical data, a fast algorithm based on OpenCL was proposed in this paper. OpenCL is an open standard supported by a majority of graphics processing unit (GPU) and operating systems. Based on this protocol, a fast-parallel algorithm, OpenCLSampEn, was proposed for sample entropy calculation. A series of 24-hour heartbeat data were used to verify the robustness of the algorithm. Experimental results showed that OpenCLSampEn exhibits great accelerating performance. With common parameters, this algorithm can reduce the execution time to 1/75 of the base algorithm when the signal length is larger than 60,000. OpenCLSampEn also exhibits robustness for different embedding dimensions, tolerance thresholds, scales and operating systems. In addition, an R package of the algorithm is provided in GitHub. We proposed a sample entropy fast algorithm based on OpenCL that exhibits significant improvement for the computation performance of sample entropy. The algorithm has broad utility in sample entropy when facing the challenge of future rapid growth in the quantity of continuous clinical and physiological signals.

The increasing significance of technology in daily lives led to the need for the development of convenient methods of human-computer interaction (HCI). Given that the existing HCI approaches exhibit various limitations, hand gesture recognition-based HCI may serve as a more intuitive mode of human-machine interaction in many situations. In addition, the system has to be deployable on low-power devices for applicability in broadly defined Internet of Things (IoT) and smart home solutions. Recent advances exhibit the potential of deep learning models for gesture classification, whereas they are still limited to high-performance hardware. Embedded neural network accelerators are constrained in terms of available memory, central processing unit (CPU) clock speed, graphics processing unit (GPU) performance, and a number of supported operations. The aforementioned problems are addressed in this paper by namely two approaches - simplifying the signal processing pipeline to avoid recurrent structures and efficient topological design. This paper employs an intuitive scheme allowing for the generation of the data in the compressed form from the sequence of range-Doppler images (RDI). Thus, it allows for the design of a neural classifier avoiding the usage of recurrent layers. The proposed framework has been optimized for Intel® Neural Compute Stick 2 (Intel® NCS 2), at the same time achieving promising classification accuracy of 97.57%. To confirm the robustness of the proposed algorithm, five independent persons have been involved in the algorithm testing process.

With the explosive growth of scientific data, significant challenges exist with respect to the interaction of large volumetric datasets. To solve these problems, we propose a visualization algorithm based on the Hilbert R-tree improved by the clustering algorithm using K-means (CUK) and a stacked long short-term memory (LSTM) model to quickly display massive data. First, we use the Hilbert R-tree optimized by the CUK to quickly store unevenly distributed data and build a fast index for the massive data. Then, we determine the position of the current point of view and use the stacked LSTM model to predict the next point of view. According to the location of two points, we divide the visible area. Finally, according to the preloading strategy, we import the data into the cache area of the graphics processing unit (GPU), which greatly realizes smoother rendering data and large-scale data interaction visualization. The experimental results showed that the proposed algorithm can quickly and accurately draw large volumetric data with high quality while guaranteeing rendering quality.

This paper considers the problem of exact accelerated algorithms for the K-means clustering of low-dimensional data on modern multi-core systems. A version of the filtering algorithm parallelized using the OpenMP (Open Multi-Processing) standard is proposed. The algorithm employs a kd-tree structure to skip some unnecessary calculations between cluster centroids and feature vectors. In our approach, both the kd-tree construction and the iterations of the K-means are parallelized using the OpenMP tasking mechanism. A new task is created for a recursive call performed during kd-tree construction and traversal. The tasks are executed in parallel by the cores of a shared-memory system. In computational experiments, we evaluated the parallel efficiency of our approach and compared its performance to the parallel Lloyd’s method, a GPU (Graphics Processing Unit) formulation of the K-means algorithm, and two parallel triangle inequality-based algorithms intended for low-dimensional data. The evaluation was performed on six synthetic datasets from two distributions and seven real-life datasets. The experiments, executed on a 24-core system, indicated that our version of the filtering algorithm had satisfactory or high parallel efficiency. Its runtime was much shorter than those of competing algorithms. However, the advantage of the parallel filtering algorithm decreased rapidly as the dimension of data increased.

Deep Neural Networks (DNNs) are the preferred choice for image-based machine learning applications in several domains. However, DNNs are vulnerable to adversarial attacks, that are carefully-crafted perturbations introduced on input images to fool a DNN model. Adversarial attacks may prevent the application of DNNs in security-critical tasks: consequently, relevant research effort is put in securing DNNs. Typical approaches either increase model robustness, or add detection capabilities in the model, or operate on the input data. Instead, in this paper we propose to detect ongoing attacks through monitoring performance indicators of the underlying Graphics Processing Unit (GPU). In fact, adversarial attacks generate images that activate neurons of DNNs in a different way than legitimate images. This also causes an alteration of GPU activities, that can be observed through software monitors and anomaly detectors. This paper presents our monitoring and detection system, and an extensive experimental analysis that includes a total of 14 adversarial attacks, 3 datasets, and 12 models. Results show that, despite limitations on the monitoring resolution, adversarial attacks can be detected in most cases, with peaks of detection accuracy above 90%.

The extended use of mobile multimedia devices in applications like gaming, 3D video and audio reproduction, immersive teleconferencing, or virtual and augmented reality, is demanding efficient algorithms and methodologies. All these applications require real-time spatial audio engines with the capability of dealing with intensive signal processing operations while facing a number of constraints related to computational cost, latency and energy consumption. Most mobile multimedia devices include a Graphics Processing Unit (GPU) that is primarily used to accelerate video processing tasks, providing high computational capabilities due to its inherent parallel architecture. This paper describes a scalable parallel implementation of a real-time binaural audio engine for GPU-equipped mobile devices. The engine is based on a set of head-related transfer functions (HRTFs) modelled with a parametric parallel structure, allowing efficient synthesis and interpolation while reducing the size required for HRTF data storage. Several strategies to optimize the GPU implementation are evaluated over a well-known kind of processor present in a wide range of mobile devices. In this context, we analyze both the energy consumption and real-time capabilities of the system by exploring different GPU and CPU configuration alternatives. Moreover, the implementation has been conducted using the OpenCL framework, guarantying the portability of the code. This work was supported in part by the Spanish Ministry of Economy and Competitiveness under Grant RTI2018-097045-B-C21, Grant RTI2018-097045-B-C22, Grant TIN2017-82972-R, and Grant ESP2015-68245-C4-1-P, and in part by the Universitat Jaume I Project UJI-B2019-36.

The lattice Boltzmann method has been fully discretized in space, time, and velocity; its inherent parallelism makes it outstanding for use in accelerated computation by graphics processing unit in large-scale simulations of fluid dynamics. When the lattice Boltzmann method is used to simulate a fluid system with complex geometry, the flow field is usually compressed to reduce memory consumption, and fluid nodes are accessed indirectly to improve computational efficiency. We designed a pointer array that is the same size as the flow field and is based on the Compute Unified Device Architecture platform’s unified memory technology. The addresses of the fluid nodes are stored in this array, and the other nodes, which are unallocated, are marked as null. For obtaining the coordinates of the fluid nodes in the original flow field, we stored the addresses of the pointer array units whose values were not null as part of the lattice attribute at the end of the lattice attribute array, forming a cyclic pointer structure to track geometric information. We validated the feasibility of this addressing scheme using an experimental simulation of aqueous humor in the anterior segment of the eye, and tested its performance on the graphics processing unit of Pascal, Volta, and Turing architecture. The present method carefully distributes data to generate fewer memory transactions and to reduce access times of the global memory, thus achieving approximately 18% performance improvement.

More engaging and accessible solutions that offer outstanding user experience are needed. The virtual desktop infrastructure (VDI) is the first user access part of the cloud. Therefore, the performance of the VDI has a significant influence on the network. The graphics processing unit (GPU) can accelerate performance by assigning each virtual machine a dedicated GPU for performance-boosting to improve the user experience. In this paper, we propose a high-performance VDI using an integration of a GPU on OpenStack with a PCI pass-through. It might have certain benefits over using virtualized hardware, such as lower latency, better performance, and more functionality. The evaluation and comparison of the computer processing unit (CPU) and GPU are presented among the different benchmark tools.

In order to improve the cost-effectiveness ratio, the next-generation vehicle needs to meet the requirements of reuse, while adopting a lighter structural weight, so it is necessary to realize the strength calculation and condition monitoring of key components in the digital twin. Most of the current monitoring methods are based on the characteristics of various data acquisition systems, but they need the support of a large number of flight data. The disadvantages of the above strategy can be avoided by reducing the structure of aircraft components to a finite element model and quickly checking the key components in the health management system. In order to solve the problem of fast calculation of the finite element model of the key components of the aircraft, a parallel algorithm and framework of large-scale sparse matrix preprocessing conjugate gradient method based on CUDA(Compute Unified Device Architecture) technology is proposed in the multi GPU(Graphics Processing Unit) workstation cluster environment. Once the sparse matrix is too large to be processed in a single workstation, this paper discusses how to realize the optimized data segmentation in the distributed multi-GPU computing environment. For the problem of iterative solution of matrix preprocessing, two preprocessing strategies of matrix bandwidth reduction parallelization and incomplete Cholesky decomposition are proposed, and asynchronous task concurrency and load balancing strategies are designed on the architecture. The calculation of some examples in the standard sparse matrix database shows that the algorithm and architecture proposed in this paper have the ability to solve large-scale sparse matrix quickly and efficiently, and can complete the fast strength verification of vehicle components.

Modern Graphics Processing Units (GPUs) require large hardware resources for massive parallel thread executions. In particular, modern GPUs have a large register file composed of Static Random Access Memory (SRAM). Due to the high leakage current of SRAM, the register file consumes approximately 20% of the total GPU energy. The energy efficiency of the register file becomes more critical as the throughput of GPUs increases. For more energy-efficient GPUs, the usage of non-volatile memory such as Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) as the GPU register file has been studied extensively. STT-MRAM requires a lower leakage current compared to SRAM and provides an appropriate read performance. However, using STT-MRAM directly in the GPU register file causes problems in performance and endurance because of complicated write procedures and material characteristics. To overcome these challenges, we propose a novel register file architecture and its management system for GPUs, named Hi-End, which exploits the data locality and compressibility of the register file. For STT-MRAM-based GPU register files, Hi-End increases the data write performance and endurance by caching and data compression, respectively. In our evaluation, Hi-End enhances the energy efficiency of a GPU register file by 70.02% and reduces the write operations by up to 95.98% with negligible performance degradation compared to SRAM-based register files.

With explosive era of machine learning development, human data, such as biometric images, videos, and particularly facial information, have become an essential training resource. The popularity of video surveillance systems and growing use of facial images have increased the risk of leaking personal information. On the other hand, traditional cryptography systems are still expensive, time consuming, and low security, leading to be threatened by the foreseeable attacks of quantum computers. This paper proposes a novel approach to fully protect facial images extracted from videos based on a post-quantum cryptosystem named NewHope cryptography. Applying the proposed technique to arrange input data for encryption and decryption processes significantly reduces encryption and decryption times. The proposed facial security system was successfully accelerated using data-parallel computing model on the recently launched Nvidia GTX 2080Ti Graphics Processing Unit (GPU). Average face frame extracted from video ( $190\times 190$ pixel) required only $2.2~ms$ and $2.7~ms$ total encryption and decryption times with security parameters $n=1024$ and $n=2048$ , respectively, which is approximately 9 times faster than previous approaches. Analysis results of security criteria proved that the proposed system offered comparable confidentiality to previous systems.

Designing resource-efficient deep neural networks (DNNs) is a challenging task due to the enormous diversity of applications as well as their time-consuming design, training, optimization, and evaluation cycles, especially the resource-constrained embedded systems. To address these challenges, we propose a novel DNN design framework called accuracy-and-performance-aware neural architecture search (APNAS), which can generate DNNs efficiently, as it does not require hardware devices or simulators while searching for optimized DNN model configurations that offer both inference accuracy and high execution performance. In addition, to accelerate the process of DNN generation, APNAS is built on a weight sharing and reinforcement learning-based exploration methodology, which is composed of a recurrent neural network controller as its core to generate sample DNN configurations. The reward in reinforcement learning is formulated as a configurable function to consider the sample DNNs' accuracy and cycle count required to run on a target hardware architecture. To further expedite the DNN generation process, we devise analytical models for cycle count estimation instead of running millions of DNN configurations on real hardware. We demonstrate that these analytical models are highly accurate and provide cycle count estimates identical to those of a cycle-accurate hardware simulator. Experiments that involve quantitatively varying hardware constraints demonstrate that APNAS requires only 0.55 graphics processing unit (GPU) days on a single Nvidia GTX 1080Ti GPU to generate DNNs that offer an average of 53% fewer cycles with negligible accuracy degradation (on average 3%) for image classification compared to state-of-the-art techniques.

The traditional surgical navigation system combining preoperative CT and intraoperative ultrasound is widely used in open hepatectomy, but the problem of this system is that there are some errors in terms of the precision of the time and the space during the surgery. In order to solve the above problems, this paper introduces augmented reality technology into the surgical navigation system. In order to accurately describe the biomechanical characteristics of the liver and let the navigation system perform more accurately, this paper uses Tetgen to perform tetrahedral partition on the triangle mesh data obtained after the three-dimensional CT was reconstructed, and then the surface mesh data and the internal tetrahedral data were obtained and they were used to describe a whole liver model. The surface triangle mesh data is used to render graphics and describe the surface topology change, and the internal tetrahedral data combined with mass-spring theory is used to simulate deformation. Subsequently, the ex vivo pig liver was used to experimentally verify the accuracy of gravity deformation of the liver model, and the results show that the error was mainly distributed between −2mm and −2.5mm. At the same time, this paper uses the NDI Polaris infrared tracking system to carry out precision experiments on the augmented reality module, and the measured error is 1.55± 0.29mm. Finally, various modules of the system are integrated to finish the experiment in which the ring-shaped lesions are cut from the ex vivo pig liver with the aid of augmented reality. The experimental error is 0± 1.26mm, and with the assistance of the general purpose graphics processing unit (GPGPU), the refresh rate is above 200FPS. The results prove that the liver surgery navigation system proposed in this paper is excellent in terms of real-time performance and accuracy, which can help doctors accurately locate the tumor during surgery and perform ideal resection.

The energy efficiency of accelerating hundreds of MB-large deep neural networks (DNNs) in a mobile environment is less than that of a server-class big chip accelerator because of the limited power budget, silicon area, and smaller buffer size of static random access memory associated with mobile systems. To address this challenge and provide powerful computing capability for processing large DNN models in power/resource-limited mobile systems, we propose McDRAM v2, which is a novel in-dynamic random access memory (DRAM) systolic array accelerator architecture. McDRAM v2 makes the best use of large in-DRAM bandwidths for accelerating various DNN applications. It can handle large DNN models without off-chip memory accesses, in a fast and efficient manner, by exposing the large DRAM capacity and large in-DRAM bandwidth directly to an input systolic array of a processing element matrix. Additionally, it maximizes data reuse using a systolic multiply-accumulate (MAC) structure. The proposed architecture maximizes the utilization of large-scale MAC units by judiciously exploiting the DRAM's internal bus and buffer structure. An evaluation of large DNN models in the fields of image classification, natural language processing, and recommendation systems shows that it achieves 1.7 times tera operations per second (TOPS), 3.7 times TOPS/watt, and 8.6 times TOPS/mm2 improvements over a state-of-the-art mobile graphics processing unit accelerator, and 4.1 times better energy efficiency over a state-of-the-art server-class accelerator. Moreover, it incurs a minimal overhead, i.e., a 9.7% increase in area, and uses less than 4.4 W of peak operating power.

This paper presents new parallel strategies for preprocessing and solving the issue of Boolean Satisfaction (SAT) on Heterogeneous systems of multicore and many-core CPU and Graphics Processing Unit (GPU) using Open Multi-Processor (OpenMP) and NVIDIA - CUDA. We propose exceptionally proficient and parallel techniques for SAT simplifications using the variable elimination method based on the Davis-Putnam-Logemann-Loveland (DPLL) slitting rule algorithm performed with a shared-memory model on a multicore CPU platform, where the clause elimination subsumption and the pure-literal removal techniques are completely performed on the CUDA framework. We demonstrate how efficient an evolutionary SAT solver is by using the suggested heterogeneous pre-processing, leading to important acceleration improvements in the solution's quality enhancement. The penalization of the transformative SAT solver is executed with Ant Colony Optimization (ACO) scheme utilizing CUDA. (Compute Unified Device Architecture) We perform thorough benchmarks to test the performance of our preprocessor and solver implementations against various random SAT formulas. The promoted H-SAT pre-processor scheme has gotten a speed-up of a factor 15x over the sequential implementation with statistical reductions on the original CNF which becomes up to 49% and 43% in case of literals and clauses numbers exclusively, where the H-SAT gain strength the solvability of the ACO solver by 100% in some cases.

N-1 static security analysis (SSA) is an important method for power system stability analysis that requires solving N alternating-current power flows (ACPF) for a system with N elements to obtain strictly accurate results. Past researches have shown the potential of accelerating these calculations using an iterative solver with graphics processing unit (GPU). This paper proposes a GPU-based N-1 SSA algorithm with the preconditioned conjugate gradient (PCG) method. First, a shared preconditioner is selected to accelerate preprocessing of the iterative method for fast decoupled power flow (FDPF) in N-1 SSA. Second, it proposes a GPU-based batch-PCG solver, which packages a massive number of PCG subtasks into a large-scale problem to achieve a higher degree of parallelism and better coalesced memory accesses. Finally, the paper presents a novel GPU-accelerated batch-PCG solution for N-1 SSA. Case studies on a practical 10828-bus system show that the GPU-based N-1 SSA algorithm with the batch-PCG solver is 4.90 times faster than a sequential algorithm on an 8-core CPU. This demonstrates the potential of the GPU-based high-performance SSA solution with the PCG method under a batch framework.

The computing power provided by the edge device is becoming increasingly improved in recent days, largely due to the technological development that realizes accelerators with a great amount of hardware parallelism. Thanks to the enhanced computing power, the application domain of the edge device is greatly expanding so that it is capable of performing new tasks previously inconceivable. In this paper, we investigate the potentials of the state-of-the-art edge devices in the context of scientific computing. We implement and perform stochastic biochemical simulation on a small cluster of modern, GPU-accelerated edge systems to examine the computational capability of the device. In addition, we perform and analyze the NAS Parallel Benchmarks (NPB) performance on the edge device. By comparing the performance of the edge device with other GPU (graphics processing unit) and CPU based systems across different platforms, we evaluate the applicability and usefulness of the modern hardware-accelerated edge devices in the scientific computing domain.

The demand for on-line analyzing of internet traffic for both security and QoS consideration directly increases as a function of using diverse applications and as malicious attacks increase. This paper presents a new fast parallel packet classification algorithm based on entropy hashing. The algorithm uses a one-level hashing data structure and enables partitioning a very large rules-set into smaller uniformly distributed sub-rules look-up tables based on maximum entropy and Most Significant Bit (MSB) pattern hash keys. This minimizes the classifier searches only to the relevant appropriate look-up table using the same hash key, and therefore significantly shortens the classification process. A further speed-up factor is achieved by parallelizing the classification algorithm using Nvidia Graphics Processing Unit (GPU). The proposed algorithm is applied to both ACL and FW applications using common synthetic rules-sets of size up to 500k rules. The simulation results show that the proposed algorithm outperforms existing classifiers in terms of both speed up and memory utilization. The required memory size is significantly reduced, and a classification speed-up factor of up to 200 is demonstrated compared to a similar serial approach.

The game of GO has long been regarded as the most challenging game for artificial intelligence because of its enormous search space and the difficulty of evaluating its board positions. In early 2016, the defeat of Lee Sedol by AlphaGo became the milestone of artificial intelligence. AlphaGo’s success lies in that it efficiently combines policy and value networks with Monte Carlo tree search (MCTS). And these deep convolutional neural networks (DCNNs) are trained by the combination of supervised learning and reinforcement learning. However, large convolution operations are computationally-intensive and typically require a powerful computing platform, for example, a graphics processing unit (GPU). Therefore, it is challenging to apply DCCNs in resource-limited embedded systems. Field programmable gate array (FPGA) is proposed to be an appropriate solution to implement real-time DCCNs models. However, the limited bandwidth and on-chip memory storage are the bottlenecks for DCCNs acceleration. In this article, an AlphaGo Policy Network is designed, and efficient hardware architectures are proposed to accelerate the DCCN model. The accelerator can be fit into different FPGAs, providing the balancing between processing speed and hardware resources. As an example, the AlphaGo Policy Network is implemented on Xilinx design suite VCU118, and the results show that our implementation achieved a performance of 3036.32 GOPS and achieved up to 56x speedup compared to CPU and 22.4x speedup compared to GPU.

The SKA (Square Kilometre Array) radio telescope will become the most sensitive telescope by correlating a large number of antenna nodes to form a giant antenna array. The data generated from such a large number of antenna nodes will pose a huge storage problem and require real-time data processing to make the best use of data, and the SKA Scientific Data Processing becomes the bottleneck of the whole processing flow. However, the existing high-performance CPU- and GPU (Graphics Processing Unit)-based solutions cannot satisfy the performance requirements and power budget requirements well [1] . Due to the consideration of the high energy efficiency of hardware accelerators and the flexibility and cost of prototype design, in this paper, we explore the FPGA(Field Programmable Gate Array)-based prototype of one of the most computationally demanding procedures in SKA scientific data processing: degridding. Through the analysis of algorithm behavior and bottlenecks, we design and optimize the memory architecture and computing logic of an FPGA-based prototype. Besides, with the consideration of the relations between the required data of processing multiple spectral channels, we reuse the shared data in processing neighboring spectral channels, and the performance further improves. The functionality and performance of our design have been verified on the target FPGA board, and the software-based benchmarks were also measured on comparable CPU and GPU platforms, indicating that the FPGA-based prototype achieves 2.74 times and 2.03 times speedup, 7.64 times and 7.42 times energy efficiency than the MPI(Message Passing Interface)-based CPU benchmark and the CUDA (Compute Unified Device Architecture)-based GPU benchmark, respectively.

Autonomous driving is the main application of Internet of Things (IoT) technology in the field of intelligent transportation. In autonomous driving, self-driving cars will avoid changing lanes in a short distance. When the self-driving car executes the follow-up instruction, the road smoothness in front of the car will affect the driving safety and comfort of the car. The real-time acquisition of road information in front of driving will help the self-driving car adjust driving behavior. However, other vehicles on the road will lead to the failure of Light Detection And Ranging (LiDAR) detectors to obtain complete road point cloud data. The incomplete road point cloud data need to be imputated to avoid potential misjudgements of the road conditions. Currently, little research work specifically focuses on imputating the incomplete road point cloud data that are caused by obstacle vehicles. In this paper, we propose a fast method to imputate the incomplete road point cloud data using a Graphics Processing Unit (GPU)-based parallel Inverse Distance Weighted (IDW) interpolation algorithm to enhance the safety of autonomous driving. To evaluate the performance of the proposed method, two groups of experiments are conducted. The experimental results indicate the following: (1) the known point cloud data within 5 meters around the obstacle vehicle are sufficient to guarantee the imputation accuracy; (2) when the weight parameter of the IDW interpolation is 4, the efficiency and accuracy of the imputation can be optimally balanced; and (3) it takes approximately 0.6 seconds to imputate the incomplete dataset consisting of 15 million points, while the imputation error is approximately 5 millimeters. The proposed method is capable of efficiently and effectively imputating the incomplete road point cloud data that are induced by obstacle vehicles and outperforms other interpolation algorithms and machine learning algorithms.

Partial registration for point clouds plays an important role in various fields such as 3D mapping reconstruction, remote sensing, unmanned driving, and cultural heritage protection. Unfortunately, partial registration is challenging due to difficulties such as the low overlap ratio of two point clouds and the perturbation in the orderless and sparse 3D point clouds. Thus, a variety of the 3D shape context descriptors are introduced for finding the optimal matching. However, extracting geometric features and descriptors are time consuming and easily degenerated by noise. To overcome these problems, we introduce a parallel coarse-to-fine partial registration method. Our contributions can be summarized as: Firstly, a robust coarse trimmed method is proposed to estimate the coarse overlap area and the initial transformation via fast bilateral denoising and parallel point feature histogram (PPFH) descriptor aligning. Secondly, an accelerated fine registration procedure is conducted by a parallel trimmed iterative closest point (PTrICP) method. Moreover, most parts of our coarse-to-fine workflow are accelerated under the Graphics Processing Unit (GPU) parallel execution mode for efficiency. Thirdly, we extend our method from the rigid registration to the isotropic scaling registration, which improves its applicability. Experiments have demonstrated that our method is feasible and robust in various situations, including the low overlap ratio, outlier, noise and scaling.

Intelligent robotic prostheses employ pattern recognition techniques in their construction and, for this, adopt several approaches of Artificial Intelligence (AI). The study created a system called BioPatRec-Py (inspired by BioPatRec) that implements the Convolutional Neural Network (CNN) and Long Short-Term Memory (LSTM) in a parallel hardware, using a lightweight architecture. The introduced system employed a set of strategies to make the classification process homogeneous, reduce training time and variability. The methodology fed the algorithm with features instead of the raw signal, providing the network with information that describes the movement (level of muscle activation, magnitude, amplitude, power, among others). The research utilized an adaptive Kaufman filter to remove noise from the series of features and adopted a quantile normalization system to make the distribution uniform and facilitate the training process. It was possible to train a generic network capable of operating in the entire population analyzed. Collective training is the main contribution of the research, as it allows the prosthesis to function on various individuals and potentially under different conditions. The individually evaluated networks reached 97.44% average accuracy with 0.69 seconds of training. The global model achieved an accuracy of 97.83% with a training time of 4.01 seconds.

As one of the most popular accelerators, the graphics processing unit (GPU) has been extensively adopted throughout the world. With the burst of new applications and the growing scale of data, co-running applications on limited GPU resources has become increasingly important due to its dramatic improvement in overall system efficiency. Quality of service (QoS) support among concurrent general-purpose GPU (GPGPU) applications is currently one of the most trending research topics. Prior efforts have been focused on providing QoS support either with OS-level or device-level scheduling methods. Each of these scheduling methods possesses pros and cons and may be unable to independently cover all the scheduling cases. In this paper, we propose a cooperative QoS scheduling scheme (C-QoS) that consists of operating-system-level (OS-level) scheduling and device-level scheduling. Our proposed scheme can control the progress of a kernel and provide thorough QoS support for concurrent applications in multitasking GPUs. Due to the accurate resource management of the copy engine and execution engine, C-QoS achieves QoS goals 23.33% more often than state-of-the-art QoS support mechanisms. The results demonstrate that cooperative methods achieve 17.27% higher system utilization than uncooperative methods.

With the widespread use of smart technologies, graphics processing unit (GPU) power-optimization issues are becoming increasingly important. Many researchers have tried to use dynamic voltage and frequency scaling (DVFS) technology to optimize a GPU's internal energy consumption. However, DVFS energy management often has difficulty balancing GPU performance and energy efficiency. This paper aims to implement a DVFS energy management strategy. We constructed a new type of neural network to a GPU-based energy management scheme, implemented the global-based DVFS model, and explored its implementation details. Using a master-slave model, we built a global energy control solution strategy. This strategy performs global collaborative DVFS adjustments on the GPU's energy consumption module based on task characteristics. Through the software construction and implementation of the global-based DVFS model, we proved that the strategy improves the GPU performance while improving the GPU's energy efficiency. We conducted performance and energy tests on three GPUs on the Tesla, Fermi, and Kepler platforms. The experiments showed that this strategy improved the performance and power consumption of GPUs based on each of the platforms.

The application of network function virtualization (NFV) and software-defined networks (SDNs) to optical access systems continues to attract a lot of attention. Their use on general-purpose hardware allows for cost-effective implementation and quick response to functional requirements. This paper demonstrates the softwarization of the complete downstream physical (PHY)-layer functions of the optical line terminal (OLT), including a scrambler, which uses a serial processing algorithm that cannot be parallelized by a general-purpose graphics processing unit (GPU). We propose CPU-GPU cooperative implementation architecture that softwarizes the complete 10G-EPON OLT downstream PHY. We achieve 10.3125-Gbps real-time performance through experiments for the first time.

Deep learning techniques have attracted much attention in the radar automatic target recognition. In this paper, we investigate an acceleration method of the convolutional neural network (CNN) on the field-programmable gate array (FPGA) for the embedded application of the millimeter-wave (mmW) radar-based human activity classification. Considering the micro-Doppler effect caused by a person's body movements, the spectrogram of mmW radar echoes is adopted as the CNN input. After that, according to the CNN architecture and the properties of the FPGA implementation, several parallel processing strategies are designed as well as data quantization and optimization of classification decision to accelerate the CNN execution. Finally, comparative experiments and discussions are carried out based on a measured dataset of nine individuals with four different actions by using a 77-GHz mmW radar. The results show that the proposed method not only maintains the high classification accuracy but also improves its execution speed, memory requirement, and power consumption. Specifically, compared with the implementation of the same network model on a graphics processing unit, it could achieve the speedup of about 30.42% at the cost of the classification accuracy loss of only 0.27%.

General purpose graphics processing unit (GPGPU) has a great advantage in parallel computation, which is appropriate in the development of signal simulators for global navigation satellite system (GNSS) signals. Real-time software signal simulators for BeiDou navigation satellite system (BDS) signals, including navigation signals and radio determination satellite service (RDSS) signals, are developed in this paper. The characteristics of the continuous signal simulation and the burst signal simulation are considered in the development of GPU algorithms. The GPU algorithm optimization considers memory usage, signal combination method, and GPU block design under the goal of the least time consumption. To get the best GPU block design, a generalized block design model is built in this paper. The optimized GPU block parameters are got for the BDS B1 signal simulation and the RDSS signal simulation, separately. For the BDS B1 simulation, when the parameters are not optimized, the time consumption is more than three times of the optimized result. For the RDSS signal simulation, this value is 4.5 times. The correctness of the signals is verified in many aspects, including the power spectral density (PSD) and the pseudo range precision.

Brain extraction is a process of removing non-brain tissue in the brain magnetic resonance (MR) images and serves as a first step towards more delicate brain segmentation. Although many brain extraction methods have been proposed in the literature, most of them are either laborious or time consuming, and lack of instant visualization. This leads to a time lag between image acquisition and comprehensive visualization. Especially for intraoperative image based neurosurgery navigation, the time lag from image acquisition to brain visualization should be reduced as much as possible. In this paper, we propose an end-to-end fast brain extraction and visualization framework. The input is a T1-weighted MR volume and the output is comprehensive brain visualization. An improved brain extraction tool (BET) algorithm is proposed to evolve a 3D active mesh model to fit the brain surface in the 3D image. Then the brain mask is generated per slice using a polygon fill algorithm. At last, a ray-casting volume rendering algorithm is used to visualize the brain surface with the help of the generated mask. All the operations are performed using the modern OpenGL pipelines running on a graphics processing unit (GPU). Experiments were performed on two publicly available datasets and one clinical dataset to compare our method with five state-of-the-art methods including the original BET in terms of segmentation accuracy and time cost. Our method achieved mean Dice coefficients of 96.8%, 97.1%, 98.5% and mean time cost of 361 ms, 341 ms, 502 ms on the three datasets, outperforming all the other methods.

Three-dimensional (3D) point clouds are important for many applications, including object tracking and 3D scene reconstruction. Point clouds are usually obtained from laser scanners, but their high cost impedes the widespread adoption of this technology. We propose a method to generate the 3D point cloud corresponding to a single red–green–blue (RGB) image. The method retrieves high-quality 3D data from two-dimensional (2D) images captured by conventional cameras, which are generally less expensive. The proposed method comprises two stages. First, a generative adversarial network generates a depth image estimation from a single RGB image. Then, the 3D point cloud is calculated from the depth image. The estimation relies on the parameters of the depth camera employed to generate the training data. The experimental results verify that the proposed method provides high-quality 3D point clouds from single 2D images. Moreover, the method does not require a PC with outstanding computational resources, further reducing implementation costs, as only a moderate-capacity graphics processing unit can efficiently handle the calculations.

The 3-D reconstruction involves the construction of a 3-D model from a set of images. The 3-D reconstruction has varied uses that include 3-D printing, the generation of 3-D models that can be shared through social media, and more. The 3-D reconstruction involves complex computations in mobile phones that must determine the pose estimation. The pose estimation involves the process of transforming a 2-D object into 3-D space. Once the pose estimation is done, then the mesh generation is performed using the graphics processing unit. This helps render the 3-D object. The competitive advantages of using hardware processors are to accelerate the intensive computation using graphics processors and digital signal processors. The stated problem that this technical paper addresses is the need for a reliable automated test for the 3-D reconstruction feature. The solution to this problem involved the design and development of an automated test system using a programmable robotic arm and rotor for precisely testing the quality of 3-D reconstruction features. The 3-D reconstruction testing involves using a robotic arm lab to accurately test the algorithmic integrity and end-to-end validation of the generated 3-D models. The robotic arm can move the hardware at different panning speeds, specific angles, fixed distances from the object, and more. The ability to reproduce the scanning at a fixed distance and the same panning speed helps to generate test results that can be benchmarked by different software builds. The 3-D reconstruction also requires a depth sensor to be mounted onto the device under examination. We use this robotic arm lab for functional, high performance, and stable validation of the 3-D reconstruction feature. This paper addresses the computer vision use case testing for 3-D reconstruction features and how we have used the robotic arm lab for automating these use cases.

In graphics processing unit ( GPU ) computing community, bitonic mergesort (BM) is recognized as one of the most investigated sorting algorithms. It is specially designed for parallel architectures, requires minor inter-process communication, can be implemented in-place, and is logically appropriate for single instructions multiple data platforms. In addition, GPUs have shown tremendous improvements in power and performance efficiency and thus have become essential ingredients in pursuit of the prospective exascale systems whose major obstacle is the excessive power consumption. In a recent research work, we found that fundamental software building blocks can offer a reasonable amount of power and energy saving that can offer new ways to tackle the power obstacle of the prospective exascale systems. We evaluated average peak power , average energy , and average kernel runtime of BM under various workloads and compared it with advanced quicksort (AQ) . The results showed that BM outperformed AQ based on all the three metrics in most cases. In this paper, we further investigate BM to identify the factors that result in its underlying power and energy efficiency advantage over AQ. We analyze the power and energy efficiency of BM and AQ based on their performance evaluation on NVIDIA K40 GPU. The performance of both the algorithms is investigated using various experiments offered by NVIDIA Nsight Visual Studio .