35 results on '"Sunil P. Khatri"'
Search Results
2. NIST-Lite: Randomness Testing of RNGs on an Energy-Constrained Platform.
3. CIDAN: Computing in DRAM with Artificial Neurons.
4. Scaled Population Subtraction for Approximate Computing.
5. A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells.
6. Threshold Logic in a Flash.
7. A Plain-Text Incremental Compression (PIC) Technique with Fast Lookup Ability.
8. Synchronization of Ring-Based Resonant Standing Wave Oscillators for 3D Clocking Applications.
9. Fast, Ring-Based Design of 3D Stacked DRAM.
10. An FPGA-Based Coprocessor for Hash Unit Acceleration.
11. Implementing low power digital circuits using flash devices.
12. A novel hardware hash unit design for modern microprocessors.
13. Exploring static and dynamic flash-based FPGA design topologies.
14. Exploring the viability of stochastic computing.
15. An area-efficient Ternary CAM design using floating gate transistors.
16. An asynchronous Network-on-Chip router with low standby power.
17. A low-jitter phase-locked resonant clock generation and distribution scheme.
18. Noise-based algorithms for functional equivalence and tautology checking.
19. An efficient arithmetic Sum-of-Product (SOP) based multiplication approach for FIR filters and DFT.
20. Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening.
21. 3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit.
22. A PLL design based on a standing wave resonant oscillator.
23. A radiation tolerant Phase Locked Loop design for digital electronics.
24. On-chip bidirectional wiring for heavily pipelined systems using network coding.
25. A robust pulsed flip-flop and its use in enhanced scan design.
26. A novel, highly SEU tolerant digital circuit design approach.
27. An Efficient, Scalable Hardware Engine for Boolean SATisfiability.
28. CMOS Comparators for High-Speed and Low-Power Applications.
29. On the Improvement of Statistical Static Timing Analysis.
30. Minimum Energy Near-threshold Network of PLA based Design.
31. X-Routing using Two Manhattan Route Instances.
32. Broadband Impedance Matching for Inductive Interconnect in VLSI Packages.
33. Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks.
34. Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design.
35. A novel cryptographic key exchange scheme using resistors.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.