10 results on '"Per Stenström"'
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2. ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness.
3. RADAR: Runtime-assisted dead region management for last-level caches.
4. π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory.
5. An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors.
6. The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches.
7. A Prefetching Technique for Irregular Accesses to Linked Data Structures.
8. Performance Evaluation of a Cluster-Based Multiprocessor Built from ATM Switches and Bus-Based Multiprocessor Servers.
9. Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors.
10. Chip-multiprocessing and beyond.
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