1. Effects of Interfacial Dielectric Layers on the Electrical Performance of Top-Gate In-Ga-Zn-Oxide Thin-Film Transistors
- Author
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Shinhyuk Yang, Jeong-Min Lee, Jong-Ho Lee, Sung Min Yoon, Chi-Sun Hwang, Kyoung Ik Cho, Woo-Seok Cheong, Sang-Hee Ko Park, Chun-Won Byun, and Sung Mook Chung
- Subjects
Materials science ,General Computer Science ,business.industry ,Electrical engineering ,Oxide ,Dielectric ,Electronic, Optical and Magnetic Materials ,Stress (mechanics) ,Compensation effect ,chemistry.chemical_compound ,chemistry ,Thin-film transistor ,Optoelectronics ,Degradation (geology) ,Electrical performance ,Atomic ratio ,Electrical and Electronic Engineering ,business - Abstract
We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top-gate In-Ga-Znoxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below 200°C, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as Si3N4 and Al2O3, the electrical properties are analyzed. After post-annealing at 200°C for 1 hour in an O2 ambient, the sub-threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative-bias stress tests on TFTs with a Si3N4 IDL, the degradation sources are closely related to unstable bond states, such as Si-based broken bonds and hydrogenbased bonds. From constant-current stress tests of Id = 3 µA, an IGZO-TFT with heat-treated Si3N4 IDL shows a good stability performance, which is attributed to the compensation effect of the original charge-injection and electron-trapping behavior.
- Published
- 2009
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