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We propose a substrate with high thermal conductivity, manufactured by the low‐temperature co‐fired ceramic (LTCC) multilayer circuit process technology, as a new DC/DC converter platform for power electronics applications. We compare the reliability and power conversion efficiency of a converter using the LTCC substrate with the one using a conventional printed circuit board (PCB) substrate, to demonstrate the superior characteristics of the LTCC substrates. The power conversion efficiencies of the LTCC‐ and PCB‐based synchronous buck converters are 95.5% and 94.5%, respectively, while those of nonsynchronous buck converters are 92.5% and 91.3%, respectively, at an output power of 100 W. To verify the reliability of the LTCC‐based converter, two types of tests were conducted. Storage temperature tests were conducted at −20 °C and 85 °C for 100 h each. The variation in efficiency after the tests was less than 0.3%. A working temperature test was conducted for 60 min, and the temperature of the converter was saturated at 58.2 °C without a decrease in efficiency. These results demonstrate the applicability of LTCC as a substrate for power conversion systems.

We propose a multilayered‐substrate‐based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost‐effective, low‐temperature co‐fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high‐temperature storage life and temperature humidity bias. At 175 °C, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 μA up to a reverse voltage of 980 V. The measured maximum reverse current (IRM), reverse recovery time (Trr), and reverse recovery charge (Qrr) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to 300 A/μs.

We propose pulse-mode dynamic Ron measurement as a method for analyzing the effect of stress on large-scale high-power AlGaN/GaN HFETs. The measurements were carried out under the soft-switching condition (zero-voltage switching) and aimed to minimize the self-heating problem that exists with the conventional hard-switching measurement. The dynamic Ron of the fabricated AlGaN/GaN MIS-HFETs was measured under different stabilization time conditions. To do so, the drain-gate bias is set to zero after applying the off-state stress. As the stabilization time increased from 0.1 μs to 100 ms, the dynamic Ron decreased from 160 Ω to 2 Ω. This method will be useful in developing high-performance GaN power FETs suitable for use in high-efficiency converter/inverter topology design. [ABSTRACT FROM AUTHOR]

In this paper, we present the design and characterization analysis of a cascode GaN field-effect transistor (FET) for switching power conversion systems. To enable normallyoff operation, a cascode GaN FET employs a low breakdown voltage (BV) enhancement-mode Si metaloxide-semiconductor FET and a high-BV depletion-mode (D-mode) GaN FET. This paper demonstrates a normallyon D-mode GaN FET with high power density and high switching frequency, and presents a theoretical analysis of a hybrid cascode GaN FET design. A TO-254 packaged FET provides a drain current of 6.04 A at a drain voltage of 2 V, a BV of 520 V at a drain leakage current of 250 μA, and an on-resistance of 331 mΩ. Finally, a boost converter is used to evaluate the performance of the cascode GaN FET in power conversion applications. [ABSTRACT FROM AUTHOR]

In this paper, we present the design and characterization analysis of cascode gallium nitride (GaN) field effect transistor (FET) for switching power conversion systems. To enable normally-off operation, a cascode GaN FET employs a low breakdown voltage (BV) enhancementmode (E-mode) silicon (Si) metal-oxide-semiconductor FET (MOSFET) and high BV depletion-mode (D-mode) GaN FET. This paper demonstrates normally-on D-mode GaN FET with high power density and high switching frequency and presents theoretical analysis for hybrid cascode GaN FET design. TO-254 packaged FET provides a drain current of 6.04 A at drain voltage of 2 V, BV of 520 V at drain leakage current of 250 uA, and onresistance of 331 mO. Finally, a boost converter is used to evaluate the performance of the cascode GaN FET in power conversion applications. [ABSTRACT FROM AUTHOR]

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) field-effect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively. [ABSTRACT FROM AUTHOR]