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In this work, a novel asymmetric T/R switch is proposed. The operating principle and design equations of the proposed T/R switch topology are presented. Based on the proposed circuit topology, an X‐band asymmetric T/R switch is designed in 0.18‐µm CMOS. From 9 to 11 GHz, the measured isolation is higher than 32 dB and the measured insertion loss is less than 1.87 dB for the TX mode. At 10 GHz, the measured TX‐mode IP1dB$I\!P_\mathrm{1dB}$ is higher than 36 dBm. [ABSTRACT FROM AUTHOR]

This Letter presents for the first time radio frequency (RF) reliability studies of fully integrated CMOS RF integrated circuits (RFICs) for next generation wireless communication applications involving conformal bodies where wireless communication RFICs will be embedded on ultra‐thin flexible packages. As a test case, RF characteristics of a CMOS voltage‐controlled oscillator (VCO) chip with multiple die‐substrate thicknesses were measured and results are analysed. The CMOS VCO chip under study was designed and fabricated using 180 nm RF‐CMOS process. Reliability of performances of the VCO chips are characterised and results are compared before and after die thinning from 250 to 50, 35, and 25 μm, respectively. Critical RF performance parameters such as frequency of oscillation, output power, and phase noise are considered for analysis, respectively. All the dies are placed face‐up for probing on the top of a metal chuck with ground connection inside the micro‐chamber of a probe station. While the deviations of frequency and output power are within ±1% and ±1 dB, respectively, due to the die thinning affect, the phase noise deteriorations are observed significant. It confirms the well‐known fact of phase noise sensitiveness to the substrate thickness due to the leakage and SOI CMOS is discussed widely to minimise these parasitic effects. [ABSTRACT FROM AUTHOR]

A semi‐passive charge‐sharing complex bandpass filter employing positive feedback technique is proposed to control bandwidth at different centre frequencies. In contrast to the previous arts, bandwidth can be changed independent of centre frequency without any rise in the number of clock phases and switches. Also, insightful continuous‐time model and block diagram of the proposed filter have been presented. The results of simulation carried out with 0.18 µm CMOS technology at 200 MHz reference frequency for centre frequencies of 10 and 20 MHz and bandwidth of 1, 3 and 7 MHz indicate the filter's ability to control the quality factor excellently. [ABSTRACT FROM AUTHOR]

An ultra‐low‐power oscillator with 0.24 pJ/cycle energy efficiency is presented, suitable for nanowatt‐level energy harvesters. The sub‐pJ/cycle energy efficiency is comparable with the lowest energy per cycle costs of prior arts and is achieved by minimising short‐circuit current with a leakage‐based delay cell and minimising dynamic power consumption with a capacitively coupled stacked structure. The proposed oscillator is fabricated in 180 nm CMOS process. Under 2.2 V supply voltage, the energy per cycle is 0.24 pJ/cycle over a frequency range of 18.2–226 kHz. [ABSTRACT FROM AUTHOR]

Fully integrated high‐voltage pulse driver with low voltage supplies and low voltage switching signals is described. Using charge redistribution for the output drive significantly reduces switching losses in the load capacitors even with the high‐voltage output swing. The proposed circuit implemented with 0.18 µm HV LDMOS technology achieves 24–55% efficiency improvement for 20 k–1 MHz 29 V pulse generation with 1.2 and 3.3 V supply voltage. [ABSTRACT FROM AUTHOR]

Massive multiple‐input multiple‐output has been broadly accepted as one of the key candidate technologies for enabling next generation (5G) wireless network. To ensure system performance, an efficient frequency dependent precoding has to be in place to pre‐compensate the frequency selective channel response in real time. This Letter presents a compact scalable frequency dependent precoding approach and its area‐efficient field programmable gate arrays (FPGA) implementation. The proposed approach has been validated and well compared with other architectures both in the Matlab/Simulink and Xilinx FPGAs. [ABSTRACT FROM AUTHOR]

For the first time, the low‐frequency kink phenomenon in the S11‐parameter of standard MOSFETs fabricated without any degradation of RF performances that exists in previous works is reported and its dependence on the gate finger number is analysed. The kink phenomenon is notable only for wide total gate width devices that show abrupt increase of a negative phase angle of the S11‐parameter in the low‐frequency region, because of a widening space between adjacent resistance circles in the Smith chart. This phase increase originated from a quadratic increase of the low‐frequency input capacitance against the gate finger number due to a constant load impedance for the S11‐parameter measurement. [ABSTRACT FROM AUTHOR]

Accurate modelling of a chip is a very important factor when analysing and predicting radio‐frequency (RF) receiver sensitivity. Chip modelling based on the tangential electromagnetic (EM) field from the near‐field measurement just above the top surface of the chip is introduced, and a methodology utilising three‐dimensional (3D) EM simulation, for predicting receiver sensitivity generated by the chip‐noise of a mobile phone, is suggested. It is worth noting here that the calculation of absolute coupling values between a noise source and an antenna is possible by using the real measured data source to obtain reliable results. [ABSTRACT FROM AUTHOR]

A technique that can increase the bandwidth of a regulated cascode (RGC) transimpedance amplifier (TIA) is presented. The proposed new RGC input topology with a positive amplifier and an inductor enables the control of the input impedance of the circuit and isolates the large input parasitic capacitance. Using this mode the dominant pole of the input node is shifted up to a high frequency, and then the bandwidth of the CMOS RGC TIA is improved. To verify the feasibility of the proposed technique, the CMOS RGC TIA is implemented using a 1P6M 0.18 µm RF CMOS technology. The 3 dB bandwidth of 4.98 GHz is measured in the presence of a 0.5 pF photodiode capacitance with a 1.8 V supply voltage. The measured result shows that the bandwidth of the TIA can increase by about 2 GHz larger than that with the conventional RGC configuration. [ABSTRACT FROM AUTHOR]

A single‐pixel sensor consisting of a dual‐lock‐in amplifier with an innovative dual‐cathode photodetector is presented. The sensor is fabricated in 0.35 µm CMOS and is designed to be integrated in a multipixel array working with a frequency shifted feedback (FSF) laser. The realised single‐pixel structure occupies an area of 120 × 100 µm² at a 58% fill factor. This pixel ensures frequency detection of the optical signal independently of its phase and power. The bandwidth of the interleaved pin photodiodes is larger than 100 MHz even for 850 nm. The sensor shows a dynamic range of ∼24 dB at a modulation frequency of 10 MHz. Signals up to 35 MHz can be detected. [ABSTRACT FROM AUTHOR]

A dual‐phase pulse‐modulated polar transmitter (PMPT) for wide power control range (PCR) applications is presented. For the validation of the proposed architecture, a radio‐frequency (RF) PMPT chip is implemented with a standard 0.18 μm 1P6M mixed‐signal CMOS process. The measurement results show that by using the proposed technique, wide PCR transmitters can be implemented accurately with low hardware requirements. An RF variable‐gain amplifier with just 21 dB of dynamic range is sufficient to pass the 80 dB PCR of the CDMA2000 standard. Compared with a conventional transmitter utilising linear power amplifiers, the proposed architecture has the potential of achieving much higher efficiency while being able to achieve chip‐level integration with eased circuit design specification. [ABSTRACT FROM AUTHOR]

An inverter‐based ultra‐low‐power, low‐noise, single‐ended to differential continuous‐time variable gain amplifier is presented for 2–6 MHz second harmonic cardiac imaging ultrasound probes in a 65 nm CMOS technology. The proposed variable gain amplifier (VGA) consists of three equal inverters and resistor arrays which form a feedback loop. To improve both the power and noise performances, the inverters operate in the sub‐threshold region by adopting a 0.5 V supply voltage. By doubling the input transconductance of the VGA, the noise figure (NF) is enhanced further. The 6‐b thermometer resistor arrays achieve a gain range of the VGA from 0 to 22 dB. The total power consumption is 55 μW, NF is 2.7 dB referred to an 8 kΩ source resistor at a centre frequency of 4 MHz. 8‐b thermometer calibration codes are added into the inverters to force the static operating point of the inverters to half of the supply voltage, which could increase the immunity of the second harmonic distortion (HD2) to the process variation. The HD2 of the proposed VGA is −60.6 dB at the 330 mV peak‐to‐peak output swing. The active size is 154 × 102 μm. [ABSTRACT FROM AUTHOR]

A high‐efficiency fast‐transient‐response V2‐controlled boost converter with a small equivalent series resistance (ESR) capacitor is presented. The proposed boost converter can achieve a fast and stable load transient response without relying on the ESR of the output capacitor. The switching frequency of the proposed boost converter is 500 kHz for a nominal 2.5–4.2 V input and a 3.3–5 V output application. Experimental results show that the transient recovery time inheriting the advantage of V2 control is shorter than 6.4 µs with the load step from 250 to 20 mA and the highest efficiency can be up to 95.4%. The proposed boost converter has been fabricated with a 0.35 µm 2P4M CMOS process, the total chip area is about 1.5 × 1.5 mm2, including the PADs. [ABSTRACT FROM AUTHOR]

Synchronised On/Off keying (S‐OOK) is a pulse modulation format where timing synchronisation pulses are embedded with each bit in the data stream resulting in a 1.5 pulse/bit format, but allowing for synchronisation and demodulation with a single block. In this reported work, the error ratio for S‐OOK symbols received in a non‐fading AWGN channel is analysed and a mathematical model aware of the physical parameters of a CMOS integrated prototype is introduced. Using this model, the S‐OOK RX sensitivity is shown to be close to that of a high‐threshold OOK RX for similar error‐ratios but assuming perfect synchronisation. [ABSTRACT FROM AUTHOR]

A report is presented on the hardware implementation of a parallel multi‐channel sampler in 0.5 μm CMOS technology. The system consists of eight parallel analogue processing channels, each one capable of modulation by a programmable binary chipping sequence. System operation is demonstrated in both Nyquist and compressive sampling of test signals. [ABSTRACT FROM AUTHOR]

High‐quality factor miniaturised inductors are prerequisites of radio frequency integrated circuit applications. This Letter presents a novel fractal stacked inductor using modified Hilbert space filling curve. The proposed inductor achieves higher inductance value and good quality factor because of mutual inductance between plural metal layers and the reduced parasitic resistance. The results show that more than double improvement in L over conventional fractal inductors and more than double improvement in quality factor value over conventional series stack construction. [ABSTRACT FROM AUTHOR]

A substrate coupling analysis flow is presented. The proposed method is fully compatible with the industry analogue/radio‐frequency design methodology, seamlessly integrates into the design environment, provides accurate estimation of the coupling effects and can model adequately all the mask design level isolation performance trends. Its accuracy is confirmed by correlating simulation results against on‐wafer silicon measurements in a 28 nm CMOS set of ring oscillators with a carrier frequency of 670 MHz. The mean error of the proposed method is 665 μV, whereas the error sigma is 765 μV. [ABSTRACT FROM AUTHOR]