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The zero‐velocity update (ZUPT) method is an effective way to reduce accumulated velocity errors of pedestrian navigation systems (PNSs). For a typical scheme, a stance phase detection module based on a fixed threshold is used to trigger the ZUPT algorithm. However, the detector is not robust enough for dynamic gait speeds. The false detection will degrade the navigation performance. In this letter, to improve the stance phase detector, the adaptive zero‐velocity detection problem is cast under dynamic gait speeds as a sequential threshold of a traditional detector inferring problem and a zero‐velocity detection framework proposed by combining a deep neural network with a traditional binary gait phase detector. Sufficient experimental results show that the proposed method outperforms other discussed learning‐based methods taking into account the trade‐off among model performance, structure, and size. Compared with the traditional method with a fixed threshold, the real‐world high‐dynamic positioning experiments show that this proposed method reduces the root mean squared error (RMSE) of absolute distance error by 48.7%, RMSE of start‐end error by 12.5%, and average RMSE of position error by 19.2%. [ABSTRACT FROM AUTHOR]

This letter proposes a measurement technique for the relative phase of a 5G new radio (NR) signal. The total radiated power (TRP) is measured to evaluate wireless equipment. However, this cannot be implemented using the near‐field measurement system owing to the digitally modulated signal. The relative phase detected by using a vector network analyser (VNA) changes significantly owing to the fast change in the signal in the time domain and the imperfect synchronisation of internal receivers of VNA. This study calculated the cumulative distribution function and medium value for the signal from the multi‐probe measurement system. The detected phase agreed well with the exact value obtained from the continuous wave signal. The proposed technique can be used for TRP calculations using the near‐to‐far field transformation. [ABSTRACT FROM AUTHOR]

A referenceless single-loop clock and data recovery (CDR) circuit with a half-rate linear phase detector (PD) and an inherent frequency acquisition technique are introduced. Cycle-slip in the half-rate linear PD and its relationship with the frequency acquisition are described in detail. The single-loop CDR consists of a conventional phase-tracking loop and a frequency-tracking unit, referred to as the cycle-slip detector. The proposed CDR is fabricated in a 28 nm CMOS process and achieves a wide capture range of 2.6 Gb/s for a PRBS31 pattern. The RMS and peak-to-peak jitter of the recovered clock are 2.40 psrms and 21.4 pspp, respectively, at 8 Gb/s. The high frequency jitter tolerance is measured as 0.3 UIpp. The CDR occupies 0.105mm2 and consumes 26mW at 8 Gb/s from a 1.0 V supply. [ABSTRACT FROM AUTHOR]

An analysis of a frequency detection capability of the Alexander phase detector is described. Based on the analysis, a simple modified implementation achieving unilateral frequency acquisition is proposed. The probability of the output occurrence and the frequency detection gain are calculated and verified by simulation. The gain curves show that the proposed phase-frequency detector (PFD) has a unilateral frequency detection capability without a range limitation. The capability is demonstrated through transient simulation of a PLL-based clock and data recovery (CDR) utilising the proposed PFD. The CDR achieves both phase and frequency acquisitions when the initial clock frequency is lower than the data rate. Moreover, the seamless transition from frequency locking to phase locking is obtained. [ABSTRACT FROM AUTHOR]

An analysis of a frequency detection capability of the Alexander phase detector is described. Based on the analysis, a simple modified implementation achieving unilateral frequency acquisition is proposed. The probability of the output occurrence and the frequency detection gain are calculated and verified by simulation. The gain curves show that the proposed phase‐frequency detector (PFD) has a unilateral frequency detection capability without a range limitation. The capability is demonstrated through transient simulation of a PLL‐based clock and data recovery (CDR) utilising the proposed PFD. The CDR achieves both phase and frequency acquisitions when the initial clock frequency is lower than the data rate. Moreover, the seamless transition from frequency locking to phase locking is obtained. [ABSTRACT FROM AUTHOR]

A hardware‐efficient slope‐error (SE) algorithm based four‐level pulse amplitude modulation (PAM4) baud rate clock and data recovery (CDR) scheme is proposed. The algorithm uses three adjacent data information to obtain slope information, thus reduces the required error samplers by 75% compared to the widely used baud rate CDR, namely, Mueller Müller (MM) CDR when working at same phase detector (PD) gain. The power efficiency of the CDR loop is improved by 36% compared to MM CDR. The proposed PAM4 baud rate CDR does not bring in extra block except for PD, which makes it easy to be extended from adaptive decision feedback equalisation. A 40 Gb/s PAM4 receiver with the proposed CDR is designed in 55 nm CMOS process. The simulated jitter tolerance of the CDR at high frequency exceeds the SONET OC‐768 JTOL mask by at least 0.35 UI at the bit error rate of 10−12. The CDR loop consumes 106 mW from a 1.2 V supply and occupies an active area of 0.1 mm2. [ABSTRACT FROM AUTHOR]

A fully‐voltage‐controlled oscillator (VCO)‐based continuous‐time (CT) Delta‐Sigma (ΔΣ) analogue‐to‐digital converter (ADC) is reported, implementing second‐order noise shaping without any analogue integrators. Traditional power‐hungry front‐end analogue integrator is replaced by a highly‐digital power‐efficient VCO‐based integrator, which is constructed by a VCO, a phase detector and a charge pump. The quantisation is executed by a VCO‐based quantiser with intrinsic noise shaping. Taking advantage of the mostly‐digital and high‐order structure, a spurious‐free dynamic range of 74 dB and a figure‐of‐merit of 52 fJ/step over a 40 MHz bandwidth are achieved by a 0‐2 multi‐stage shaping (MASH) demonstration in 40 nm CMOS. [ABSTRACT FROM AUTHOR]

A compact low‐supply‐voltage yet low‐noise digital bang–bang PLL (DBBPLL) is proposed. The bang–bang phase detector is based on a dynamic double‐tail latch which enables high time‐to‐voltage gain and low input‐referred noise under tight power‐supply headroom. The ring‐based digitally controlled oscillator (DCO) is made of multiple gm‐controlled delay units and a constant‐gm‐biased current DAC. By combining these two blocks, the DCO can now better tolerate supply noise and process variations. A prototype DBBPLL has been implemented in a mainstream 28 nm CMOS process with a compact die area of 0.014 mm2. When operating at 2.6 GHz, it consumes 2.9 mW with 0.75 V supply and achieves low in‐band phase noise of −105 dBc/Hz. [ABSTRACT FROM AUTHOR]

Flip‐flop based phase‐frequency detectors are widely used in phase‐locked loop circuits. These devices are usually assumed to behave linearly although they consist of non‐linear parts. In this work, a flip‐flop based phase‐frequency detector circuit is analysed. Analytic output signal models are derived for arbitrary input signal frequencies and phases. Exact and approximate closed‐form solutions are found for different frequency ratios. The model is validated by numerical time‐domain simulations. [ABSTRACT FROM AUTHOR]

A novel 2 × time‐difference amplifier (TDA) in 65 nm CMOS technology is presented. Unlike traditional analogue TDA, the proposed TDA, employing an all‐digital synchronous architecture, achieves 2 × TDA in a time subtracting way based on time register. Multi‐path negative skewed gated delay cells are utilised to minimise gating skew error in the time register. To make up for the delay mismatch in the two time registers, a foreground calibration scheme that calibrates the input offset of the phase detectors at the same time is applied. The TDA gain ranges from 1.99 to 2.02 over ± 150 ps input time‐difference range and the standard variation of the gain is 0.02 under various process, voltage and temperature (PVT) conditions. The simulated average of power consumption is 62 μW under 100 MHz clock frequency. [ABSTRACT FROM AUTHOR]

A phase‐locked loop (PLL) architecture based on a 2D phase comparator matrix is introduced. In its general form, multiple phases of the input reference clock are compared with multiple phases of the feedback clock, allowing for wider bandwidth (BW) and lower phase noise generation of the PLL. Based on matrix phase detector architecture, a 6.25 GHz PLL achieving 5 GHz BW and exhibiting 55 fs‐rms jitter is designed in 28 nm CMOS bulk technology. [ABSTRACT FROM AUTHOR]

A 266–2133 MHz phase shifter is proposed for LPDDR4X interface, utilising an all‐digital delay‐locked loop (DLL) and a triangular‐modulated phase interpolator (PI) to improve the jitter and linearity. The DLL consists of two kinds of DLLs: a global DLL to assist fast locking; and a local DLL which uses an adaptive‐window phase detector and a folded delay line to reduce jitter and improve linearity. The PI uses a triangular‐modulated clock waveform to achieve good linearity over a wide frequency range. The prototype chip is implemented in a 65 nm CMOS process. The measured jitter of the DLL is 3.08 psrms/19.93 pspp at 2133 MHz. The measured differential non‐linearity of the phase shifter is <0.91 LSB at 2133 MHz, and the power efficiency is about 2.7 mW/GHz. [ABSTRACT FROM AUTHOR]

An improved bang‐bang phase detector (PD) for multi Gb/s clock and data recovery (CDR) circuits is presented. The proposed PD is based on inverting the Alexander PD. In a typical subsampled CDR circuit, this Inverse Alexander PD results in a ten times better bit error rate (BER) compared with the conventional Alexander PD. Additionally, in the case of duty‐cycle distorted input data, this Inverse Alexander PD can even reach 20 times better BER compared with the conventional Alexander PD. [ABSTRACT FROM AUTHOR]

A carrier signal lock-in experiment using a 300-GHz integrated heterodyne circuit is presented. The circuit contains a single voltage-controlled oscillator with a single set of quadrature mixers that are fabricated using 250-nm InP double hetero-junction bipolar transistor technology. An external feedback loop containing packaged baseband components such as amplifiers, a phase discriminator, and a filter is connected to the integrated circuit to form a complete receiver system. For a -25 dBm of input RF signal with 3.5-GHz single-tone carrier-suppressed modulation, the receiver system responds with successful lock-in range of 110 MHz centred around 311 GHz. [ABSTRACT FROM AUTHOR]

An all‐digital phase frequency detector design capable of accepting an infinite range of input frequency differences and [0 2π] radians input phase difference is presented. The proposed phase frequency detector design minimises the dead zone, supresses unwanted output glitches, achieves a high maximum operating frequency, can drive high‐capacitive loads and avoids differential outputs. The proposed phase frequency detector takes advantage of a fast reset operation from modified tristate inverters acting as a D flip‐flop. Simulation results indicate that the design can detect input phase differences as small as 750 fs apart for all process corners at input operating frequencies of 38 kHz–2.5 GHz in 1.2 V, 90 nm CMOS technology. [ABSTRACT FROM AUTHOR]

The use of a silicon (Si)‐photodiode (Si‐PD) operating in photovoltaic mode as a tunable very high‐sensitivity phase detector of light power variations is demonstrated. This result is reached by applying to the Si‐PD an electrical modulation through an AC excitation signal without a DC reverse bias. This allows employing the synchronous demodulation technique for phase detection that shows much better performances with respect to the conventional amplitude measurements, mainly overcoming the issues related to the electrical noise and the resolution limitation due to the selected full scale. The phase variations to be detected occur between the modulating signal and the one provided by the Si‐PD as a function of the light power variations on its sensitive area. The proposed approach notably simplifies both the electronic circuitry and the optical setup, minimising the detection system complexity and size. Experimental results demonstrate that it is possible to achieve phase detection sensitivity, with respect to light power variations, of up to 410°/μW as a function of the Si‐PD settable operating conditions. Using a standard commercial lock‐in amplifier with a 0.01° phase resolution is possible to obtain a light power resolution of up to 25 pW. [ABSTRACT FROM AUTHOR]

A new robust harmonic lock detector (HLD) suitable for a wide‐range delay‐locked loop (DLL) is presented. This detector is composed of some delay indicators measuring the total delay of the DLL in real time, and it can detect the harmonic lock for a wide frequency range close to 1–20 times higher than the minimum frequency. Owing to its seamless operation without any initialising process using external reset control, it can ensure reliable lock detection despite some unusual conditions, such as frequency change, electrical surge input or power‐ground fluctuation. The proposed HLD and the DLL were designed in 0.13 µm CMOS technology, and the simulation results showed the exact harmonic lock detection and reliable DLL locking properties over the whole frequency range from 25 to 500 MHz of the input clock. [ABSTRACT FROM AUTHOR]

A 2 GHz sub‐harmonically injection‐locked phase‐locked loop (SILPLL) with a self‐aligned injection window is presented. The SILPLL adopts a mixer‐based self‐align technique to automatically adjust the injection timing, overcoming the speed limitation of the phase detection. Circuit techniques such as a symmetrical mixer and a V/I converter with mismatch cancellation are adopted to improve injection timing accuracy. Fabricated in a 180 nm CMOS technology, the SILPLL exhibits −127 dBc/Hz phase noise at 1 MHz offset and draws 6.9 mA current from a 1.8 V power supply. The measured root‐mean‐square jitter integrating from 1 kHz to 40 MHz is 214 fs and the reference spur is −61 dBc. [ABSTRACT FROM AUTHOR]

In time synchronisation systems, the code phase of the spread spectrum signal is an important characteristic that can provide users with highprecision and unambiguous observation results. However, digital code phase discriminators have limited sampling frequencies that distort the signal correlation peak and generates a zero-bias codephase estimate. In this Letter, the authors evaluate and analyse the zero-phase deviations of digital code phases. An optimal correlation interval design method, based on a code phase discriminator that can effectively suppress the zero-crossing deviation, is also proposed. The simulation results show that the proposed algorithm can reduce the deviation of 96.5% and effectively improve the measurement accuracy of the code phase. [ABSTRACT FROM AUTHOR]

Wireline communication circuits often include serialisers/deserialisers using multiphase signals for multiplexing or sampling. From a power efficiency viewpoint, configurations are desired in which a single differential clock at frequency f is distributed to decentralised multiphase generators as opposed to distribution at 2f with local frequency dividers. A bang-bang phase detector (BBPD) is presented for such a multiphase generator operated from 4 to 16 GHz. Owing to the 2-octave frequency range, a wide input phase range is required for which the BBPD may not generate false locks. This is achieved by an implementation in which down pulses at the output of a fully symmetrical set/reset latch are stretched via pulse-width extension circuitries. A sampling pulse generated from one of the input phases can then easily capture the extended down pulses across a wide input phase range to unambiguously indicate phase leading or phase lagging to the control logic of the multiphase generator. The proposed circuitry has been implemented in a 7 nm CMOS technology. A comparison to alternative BBPD approaches implemented in the same technology shows that the proposed architecture outperforms them in terms of achievable input phase range. [ABSTRACT FROM AUTHOR]

An introduction is presented which discusses several reports within the issue of the periodical on topics including piezoresistive wind speed sensor; quarter cylindrical dielectric resonator antenna and memristors.

A hardware-efficient slope-error (SE) algorithm based four-level pulse amplitude modulation (PAM4) baud rate clock and data recovery (CDR) scheme is proposed. The algorithm uses three adjacent data information to obtain slope information, thus reduces the required error samplers by 75% compared to the widely used baud rate CDR, namely, Mueller Müller (MM) CDR when working at same phase detector (PD) gain. The power efficiency of the CDR loop is improved by 36% compared to MM CDR. The proposed PAM4 baud rate CDR does not bring in extra block except for PD, which makes it easy to be extended from adaptive decision feedback equalisation. A 40 Gb/s PAM4 receiver with the proposed CDR is designed in 55 nm CMOS process. The simulated jitter tolerance of the CDR at high frequency exceeds the SONET OC-768 JTOL mask by at least 0.35 UI at the bit error rate of 10-12. The CDR loop consumes 106 mW from a 1.2 V supply and occupies an active area of 0.1 mm². [ABSTRACT FROM AUTHOR]

The authors propose and demonstrate a photonics-based wideband Doppler frequency shift (DFS) measurement scheme through inphase and quadrature detection. The system has a compact structure applying cascaded phase modulation and polarisation modulation. It is easy to implement since both the value and sign of the DFS can be estimated by simple signal processing. More importantly, the proposed scheme is suitable for both DFS measurement and direction discrimination over a very wide frequency range. In the experiment, accurate DFS measurement with a large carrier frequency range from 5 to 40 GHz is demonstrated with the measurement error kept within ±12 Hz. [ABSTRACT FROM AUTHOR]

A low-cost two-step delay locked loop (DLL) with a 20-80% input duty cycle is presented. For eliminating harmonic and zero-trap locking issues along the whole range of digital controlled delay line, a hierarchy phase detector (HPD) is proposed to compare the phase difference between input reference clock and two phase-isotonic clocks generated by sharing a common delay line. By monitoring of HPD's output, state controller can solve harmonic and zero-trap locking issues while being naturally immune to the wide range of input duty cycle. With an asymmetric edge combiner, high duty cycle correction accuracy can be achieved. The proposed DLL is implemented in 55 nm CMOS technology with a 0.00574 mm² chip area. Simulation results show that the operation range of the proposed DLL is 0.3-1.6 GHz without the occurrence of harmonic and zero-trap locking, and the range of input duty cycle is 20-80%. The power consumption is 0.76 mW at 1.6 GHz. [ABSTRACT FROM AUTHOR]

A low‐cost two‐step delay locked loop (DLL) with a 20–80% input duty cycle is presented. For eliminating harmonic and zero‐trap locking issues along the whole range of digital controlled delay line, a hierarchy phase detector (HPD) is proposed to compare the phase difference between input reference clock and two phase‐isotonic clocks generated by sharing a common delay line. By monitoring of HPD's output, state controller can solve harmonic and zero‐trap locking issues while being naturally immune to the wide range of input duty cycle. With an asymmetric edge combiner, high duty cycle correction accuracy can be achieved. The proposed DLL is implemented in 55 nm CMOS technology with a 0.00574 mm2 chip area. Simulation results show that the operation range of the proposed DLL is 0.3–1.6 GHz without the occurrence of harmonic and zero‐trap locking, and the range of input duty cycle is 20–80%. The power consumption is 0.76 mW at 1.6 GHz. [ABSTRACT FROM AUTHOR]

An interview with Marcel Kossel from IBM Research is presented talking about the paper ‘Bang-bang phase detector with wide input phase range. It mentions IBM technology focuses analogue and mixed signal integrated circuit (IC) designs for high-speed serial links used in IBM's processor chips and server systems; increasing demand for higher input/output throughput to maintain the improvement in computational performance; and concept of performing a servo loop in-phase quadrature calibration.

A phase variation detection scheme based on a SSB-AM detector for the active phased array antenna is introduced. Since the phases of arrayed elements for the active phased array antenna vary unavoidably with increase in the surrounding temperature, such shifts should be detected and compensated accordingly, for maintaining the accuracy of beam direction radiated from the phased array antenna. Simulation results show that the proposed scheme is quite feasible. [ABSTRACT FROM AUTHOR]

Three-element in-phase coherently coupled arrays of vertical cavity surface-emitting lasers (VCSELs) were fabricated using proton implantation. The arrays show excellent beam quality with a far-field divergence of 4°, while maintaining a stable in-phase mode until a maximum output power of 4 mW under continuous-wave condition. The process for the arrays is simple and the cost is low. [ABSTRACT FROM AUTHOR]