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An improved extension method based on protograph extrinsic information transfer (PEXIT) charts is proposed to design ratecompatible quasi-cyclic low-density parity-check (QC-LDPC) codes with more flexible rates and better performance. The masking matrix of the highest-rate code can first be constructed column by column to own the lowest decoding threshold. Then, an extension algorithm is proposed to obtain the masking matrices of lower-rate codes with flexible rates. Finally, the base matrices with small amount of short cycles are designed and the parity-check matrices of rate-compatible QC-LDPC codes are obtained through matrix extension. Simulations show that compared with the existing codes, the proposed codes have more flexible rates while achieving better performance. [ABSTRACT FROM AUTHOR]

Quasi-cyclic low-density parity check (QC-LDPC) codes are being widely used in communication standards, and the decoder of QC-LDPC codes requires a unique type of rotator. The unique rotator, called a multi-size cyclic-shifter (MSCS), should be able to rotate data with various sizes, and many structures have been proposed for the operation. A low-complexity, high-speed MSCS structure is proposed, in which a part of the previous smallest structure is replaced with a structure with less delay and comparable area. The synthesis results present that the proposed structure achieves not only the highest speed but also the lowest complexity after synthesis. [ABSTRACT FROM AUTHOR]

In this Letter, a new parity-check-concatenated (PCC) polar code construction that considers the number of minimum Hamming weight (MHW) codewords is proposed. The parity bits to reduce the number of MHW codewords as much as possible is successively constructed. The proposed construction can reduce the number of MHW codewords more than other codes. The results show that the proposed codes can outperform the other codes at a high signal-to-noise region. [ABSTRACT FROM AUTHOR]

From Sidon sequences, two explicit methods for constructing (2J, 2L)- regular type-II quasi-cyclic (QC) low-density parity-check (LDPC) codes are proposed without four cycles. The advantage of the new methods is two-fold: (i) compared with the existing lower bound of circulant permutation matrix (CPM) sizes above which type-II QC-LDPC codes exist without four cycles, the novel constructions enable much tighter lower bounds; and (ii) the codes constructed by the first method perform almost as well as type-II QC-LDPC codes from perfect cyclic difference set, while possessing a much more flexible CPM sizes. [ABSTRACT FROM AUTHOR]

Single‐error correction, double‐error detection (SEC–DED) codes are a type of error‐correction codes widely used in electronics to protect memory devices from data corruption. Odd‐weight‐column SEC–DED codes are a type of these codes where the parity‐check matrix is built with every column including an odd number of ones. With this approach, double errors have an even‐weight syndrome and can be differentiated from single errors and, consequently, easily detected. There are applications, such as avionics or space, where a multiple error usually affects adjacent cells. Adapting SEC–DED codes to protect against triple‐adjacent errors is interesting in these applications. A modification to existing odd‐weight‐column SEC–DED codes to add triple‐adjacent error detection (TAED), creating SEC–DED–TAED codes, is presented. The implementation of the additional triple‐adjacent detection logic for these codes can be performed with limited performance and area overhead. [ABSTRACT FROM AUTHOR]

A symbol level iterative soft decision (SD) algorithm for Reed-Solomon codes based on parity-check equations is developed. This is achieved by transforming the systematic parity-check matrix according to some rules. The rules are based on the soft reliability information matrix derived from the received vector. The symbol error rate performance of the resulting algorithm is documented through computer simulation and compared with the hard decision Berlekamp-Massey (B-M) algorithm, and the Koetter and Vardy-Guruswami and Sudan (KV-GS) algorithm. The result verifies that the iterative (SD) algorithm outperforms the KV-GS and B-M algorithms by a significant margin while maintaining a reasonable decoding time complexity level. [ABSTRACT FROM AUTHOR]

A symbol level iterative soft decision (SD) algorithm for Reed‐Solomon codes based on parity‐check equations is developed. This is achieved by transforming the systematic parity‐check matrix according to some rules. The rules are based on the soft reliability information matrix derived from the received vector. The symbol error rate performance of the resulting algorithm is documented through computer simulation and compared with the hard decision Berlekamp‐Massey (B‐M) algorithm, and the Koetter and Vardy‐Guruswami and Sudan (KV‐GS) algorithm. The result verifies that the iterative (SD) algorithm outperforms the KV‐GS and B‐M algorithms by a significant margin while maintaining a reasonable decoding time complexity level. [ABSTRACT FROM AUTHOR]

For efficient hardware implementation of QC-LDPC encoders, four types of rotate-left-accumulator (RLA) circuits are proposed. Although the performance of a type I RLA circuit is exactly identical to the most widely used shift-register-adder-accumulator (SRAA) circuit, its reasonable structure can derive the other three counterparts. Both type II and III RLA circuits are highly area efficient, and have the same speed as the SRAA circuit. Compared with these serial-in circuits, the parallel-in type IV RLA circuit is faster at the cost of more memory, and suitable for applications where generator matrices have fewer block rows or special parity-check matrices are used to encode. [ABSTRACT FROM AUTHOR]