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A technique to accurately estimate the leakage power in CMOS nanometre integrated circuits (ICs) is presented. The model has similar accuracy to SPICE and represents an important improvement with respect to previous works. The model can be used for a fast and accurate estimation of the standby power dissipated by large circuits.

I/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behaviour of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some open defects can be also detected. However, an important set of open defects escapes quiescent power supply current testing because they prevent any current elevation. As a solution, dynamic current testing is investigated. A built-in dynamic current sensor is proposed.

An off-chip monitor is presented that measures the transient supply current of CMOS ICs and provides the charge delivered to the circuit. The monitor is designed to be placed on the automatic test equipment board fixture and automate transient current supply testing. Experimental results demonstrate up to 1 GHz bandwidth operation.

A simple method to evaluate the propagation delay of complex CMOS gates computed from inverter delay models based on the nth-power law MOSFET model is presented. The method is based on a transistor collapsing technique developed for complex gates and takes into account short-channel effects, internal coupling capacitances and the body effect. The propagation delay of complex gates for a 0.18 /spl mu/m technology is evaluated, showing excellent results.

An architecture for simplifying fault diagnosis is presented. The method is applied to circuits incorporating built-in current (BIC) sensors and is based on hardware partitioning, does not increase the number of pins and is independent of the fault diagnosis heuristic at the logic level.

A test technique that uses the charge driven into the circuit computed from the transient power supply current is analysed. Experimental data are provided concerning the merits of this technique and its effectiveness at detecting open defects that do not increase the power consumption (those that cannot be detected with IDDQ).

Many integrated circuit processing defects may cause changes in the value of the quiescent power supply current. Not all of these changes are detectable using classical functional testing techniques. Testing techniques based on the quiescent power supply current inspection have been reported to be efficient in the detection of a wide set of well known physical defects (including bridges and stuck-on). Two quiescent current sensor circuits are proposed and discussed. These circuits are oriented to different testing applications such as the external functional ATE environment, and the built-in self-testing (BIST) design for both on-line and off-line strategies. >