Search

For efficient hardware implementation of QC-LDPC encoders, four types of rotate-left-accumulator (RLA) circuits are proposed. Although the performance of a type I RLA circuit is exactly identical to the most widely used shift-register-adder-accumulator (SRAA) circuit, its reasonable structure can derive the other three counterparts. Both type II and III RLA circuits are highly area efficient, and have the same speed as the SRAA circuit. Compared with these serial-in circuits, the parallel-in type IV RLA circuit is faster at the cost of more memory, and suitable for applications where generator matrices have fewer block rows or special parity-check matrices are used to encode.

Presented is a phase accumulator (PACC) for current-mode logic (CML)-based high-speed CMOS direct digital frequency synthesisers (DDFSs). The proposed PACC not only consumes low power by using an adaptive power reduction technique, but also updates frequency information within one clock period by using dual function logic gates and the charge sharing scheme that accelerates current recovery time. This work reduces power consumption by 33% compared to the conventional PACC with a pipeline depth of 8 and 32-bit FCW.

Presented is a low-power small-area pipelined phase accumulator (PACC) for direct digital frequency synthesisers (DDFSs). To minimise the number of pre-skewing flip-flops, the proposed scheme sequentially loads Frequency Control Word (FCW) input data directly to the corresponding unit accumulators without through series of flip-flops, thus reducing the power consumption as well as the chip area compared to previously reported PACCs. A 24-bit PACC using the proposed scheme is fabricated in a 0.13 µm CMOS process with built-in phase-to-amplitude mapping circuitry and a D/A converter for measurements of the PACC performance. Experimental results show that the proposed architecture reduces power consumption by 21 and 34% compared to CML-based and static CMOS-based conventional PACC designs, respectively.

A pipelined phase accumulator (PACC) for direct digital frequency synthesisers (DDFSs) is presented. A highly pipelined structure is inevitable in a PACC design to achieve high-speed performance, which causes a large number of pre-skewing flip-flops (F/Fs) and leads clock signals to be a large source of power dissipation. Since the input data do not change every single cycle, clock gating can save power by decreasing the number of unnecessary clock switching in the pre-skewing F/Fs. Sequential clock gating for pipelined PACCs is proposed. Compared with the conventional pipelined PACCs with and without clock gating, the proposed scheme reduces power dissipation by up to 55.4 and 77.2%, respectively, for the 32-bit 8-pipeline-stage PACCs.

Geometrical analysis is used to show that Hough transform (HT) space accumulator arrays (butterflies) exhibit self-similar properties. A very high resolution HT is then proposed based on this property. This method reliably overcomes the peak splitting and vote spreading problems associated with traditional high resolution HTs.

An accumulator-based digital-to-frequency (DFC) converter employing redundant signed binary addition (RSBA) is presented. RSBA is advantageous in that no carry propagation occurs resulting in constant delay regardless of operand word size. Utilising RSBA in the proposed DFC resolves the performance bottleneck in the DFC's conventional implementation and achieves extremely high frequency resolution. In addition, a new RSBA-based 8∶1 multiplexer is introduced for a complete RSBA implementation of the DFC. Experimental results show an increase of more than 3.5 times in the speed of the accumulator compared to the conventional implementation regardless of bit size of the adder.

A new design method for a triple-tunable type DDFS-driven PLL frequency synthesiser is presented. Since only a phase accumulator is used in the DDFS (direct digital frequency synthesiser), the other parts of the DDFS such as ROM and a D/A converter can be excluded using the proposed method. Therefore, performance improvements are achieved such as circuit simplicity, reduced power consumption and switching time. In addition, the output of the designed DDFS is processed to provide a jitter-free input reference to the PLL. Simulation results show the validity and performance improvements of the proposed system, compared with the conventional system.

A novel method for line detection is presented, based on a modified weighted Hough transform. A given binary image is decomposed into connected regions whose contribution to the accumulator array is determined as a function of appropriate shape descriptors. The method is successfully applied to demanding image processing and computer vision problems where the original Hough transform fails to produce satisfactory results.

A class of serial/parallel architectures for inner-product computation is described, based on carry-save accumulator arrays. In their basic form such arrays form carry-save multiply/adders. A simple modification of the coefficient feed allows flexible extension to short vector inner-product computation using distributed arithmetic. These modules may be cascaded to handle longer vectors, forming high-level VLSI digital signal processing subsystems.