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Active inductors are suitable for MMIC integration, especially for filters applications, and the definition of strategies for an efficient design of these circuits is becoming mandatory. In this work we present design considerations for the reduction of DC current in the case of an active filter design based on the use of active inductors and for high-power handling. As an example of applications, the approach is demonstrated on a two-cell, integrated active filter realized with p-HEMT technology. The filter design is based on high-Q active inductors, whose equivalent inductance and resistance can be tuned by means of varactors. The prototype was realized and tested. It operates between 1800 and 2100 MHz with a 3 dB bandwidth of 30 MHz and a rejection ratio of 30 dB at 30 MHz from the center frequency. This solution allows to obtain a P1 dB compression point of about −8 dBm and a dynamic range of 75 dB considering a bias current of 15 mA per stage.

We here present a 0.15 &micro, m CMOS high input impedance and low noise AC coupled flipped voltage follower-based amplifier for high integration level in integrated circuits in a wide range of sensing applications. With such a circuit, it is possible to achieve a high level of integration, thanks to the absence of passive resistors, and also to implement a very high input impedance without capacitive feedback thanks to bootstrap operation, thus offering a very low high-pass cutoff frequency. Simulated results with a proven and well modeled standard technology show a whole circuit input-referred noise of 5.4 &micro, Vrms. The bias voltage is &plusmn, 0.6 V with a total power consumption of the single amplifier of 20 &micro, W. The very low circuit complexity allows a very low estimated reduced area occupation giving, as a general example, the possibility of integrating an array of up to thousands of channels for biomedical applications. Detailed simulation results, PVT analysis and comparison tables are also presented in the paper.

In this paper, a new realization of electronically tunable voltage output second-order low-pass (LP) and band-pass (BP) filter is presented. The circuit has a multiple-input single-output structure, and LP and BP outputs are provided using the same structure. One electronically variable second-generation voltage conveyor (VCII), whose impedance at the Y port can be electronically varied using a control current (Icon), two capacitors, and one resistor are used. By changing the value of Icon, the impedance value at the Y port can be electronically varied; therefore, the value of ω0 can be tuned. This feature helps to reduce the number of passive components used. Interestingly, the LP and BP outputs are provided at the low-impedance Z port of the VCII, and there is no need for an extra voltage buffer for practical use. The circuit enjoys a simple realization consisting of only 24 MOS transistors. Simulation results using PSpice and 0.18 μm CMOS parameters are provided. The value of ω0 can be varied from 1.2 MHz to 1.7 MHz, while Icon varies from 0 to 50 µA, with a power consumption variation from 244 µW to 515 µW.

In this paper, a new implementation of an electronically tunable resistor-less floating inductance simulator using a second-generation voltage conveyor (VCII) is presented. The proposed circuit is resistor-free (benefiting from the intrinsic resistors at the Y terminals of the employed VCIIs) and composed of three VCIIs and a single grounded capacitor. Using a control current (Icon), the value of impedance at the Y terminal of the VCII is varied, whereby the value of the simulated inductance is tuned. The proposed circuit is designed at a transistor level using 0.18 µm TSMC CMOS parameters and ±0.9 V supply voltage. PSpice simulations are carried out to confirm the effectiveness of the proposed circuit. For a range of Icon from 0 µA to 50 µA, the value of the simulated L can be varied from −576 µH to −324 µH and from +316 µH to +576 µH for negative and positive simulators, respectively, in the frequency range of 100 kHz–3 MHz. Favorably, the value of the series resistance remains below 76 Ω. Simulation results show an error value below 4.8% and power consumption variation is from 1.64 mW to 1.92 mW. Moreover, application of the proposed circuit as a standard band-pass RLC filter is also included.

This paper presents a new realization of a grounded simulated inductor using a single dual output second-generation voltage conveyor (VCII±) as an active building block, two resistors and one grounded capacitor. The main characteristic of the proposed circuit is that the value of the series resistor can be significantly reduced. Thus, it has the property of improved low-frequency performance. Another feature is the use of a grounded capacitor that makes the proposed circuit attractive for integrated circuit (IC) realization. A simple CMOS implementation of the required VCII± is used. However, a single passive component-matching condition is required for the proposed structure. As an application example, a standard fifth-order high-pass ladder filter is also given. SPICE simulations using 0.18 μm CMOS technology parameters and a supply voltage of ±0.9 V as well as experimental verifications, are carried out to support the theory.

The use of Key Enabling Technologies (KET), in the definition of innovative systems, is a crucial point for smart industries and sustainability. The proposed work combines innovations from different fields, including industrial sustainability on the one hand, and smart electronics on the other. An innovative multifunctional panel is presented, produced with waste resulting from the industrial processing of paper and cardboard, the panel can be used for the control of safety in processing factories and for the monitoring of environmental conditions in the area, as well as the energy improvement of the building envelope. Several sensors are embedded in the panel for monitoring temperature, moisture, and localization by means of an RFID tag. In addition, the panel is battery–free, thus enhancing the installation and realization of the system. The power supply is provided by the tag reader as irradiated power, thus realizing a very low power application. Panels have been already realized and experimental tests have been performed in the laboratory.

In this paper two new first order filter topologies realizing low-pass/all-pass (LP/AP) and low-pass/high-pass (LP/HP) outputs using electronically controllable second generation voltage conveyors (CVCIIs) are presented. Unlike second generation voltage conveyors (VCII), in CVCII each performance parameter, including ports, parasitic impedances, current and/or voltage gains can be electronically varied. Here, in particular, the proposed filter topologies are based on two CVCIIs, one resistor and one capacitor. In the first topology VLP/IAP/VAP and in the second topology ILP/VLP/IHP/VHP outputs are achievable, respectively. However, the current and voltage outputs are not achievable simultaneously and a floating capacitor is used. A control current (Icon) is used to change the first CVCII Y port impedance, which sets the filter −3 dB frequency (F0) of all the outputs. Moreover, in the second topology, the gains of HP and AP outputs are electronically adjusted by means of a control voltage (Vcon). Favorably, no restricting matching condition is necessary. PSpice simulations using 0.18 µm CMOS technology and supply voltages of ±0.9V show that by changing Icon from 0.5 µA to 50 µA, F0 is varied from 89 kHz to 1 MHz. Similarly, for a Vcon variation from −0.9 V to 0.185 V, the gains of IAP and IHP vary from 30 dB to 0 dB and those of VAP and VHP vary from 100 dB to 20 dB. The total harmonic distortion (THD) is about 8%. The power consumption is from 0.385 mW to 1.057 mW.

In this paper, a novel low voltage low power CMOS second generation voltage conveyor (VCII) with an improved voltage range at both the X and Z terminals is presented. The proposed VCII is formed by a current buffer based on a class AB regulated common-gate stage and a modified rail-to-rail voltage buffer. Spice simulation results using LFoundry 0.15&nbsp, &mu, m low-Vth CMOS technology with a &plusmn, 0.9&nbsp, V supply voltage are provided to demonstrate the validity of the designed circuit. Thanks to the class AB behavior, from a bias current of 10&nbsp, &micro, A, the proposed VCII is capable of driving 0.5&nbsp, mA on the X terminal, with a total power consumption of 120 &micro, W. The allowed voltage swing on the Z terminal is at least equal to &plusmn, 0.83&nbsp, V, while on the X terminals it is &plusmn, 0.72&nbsp, V. Both DC and AC voltage and current gains are provided, and time domain simulations, where the voltage conveyor is used as a transimpedance amplifier (TIA), are also presented. A final table that summarizes the main features of the circuit, comparing them with the literature, is also given.

This paper deals with the definition and analysis of a complete electronic system for the detection and monitoring of stability characteristics in complex scenarios such as structural elements or environmental events. For instance, it may be successfully adopted to detect rockfall events on protection barriers, as well as to monitor landslides or the integrity of structures like bridges and buildings. The system is completely autonomous thanks to the implementation of an energy harvesting architecture and realizes a wireless sensor network whose nodes are auto-configurable, making it possible to freely arrange them in situ. The continuously collected data are relative to acceleration, inclination, position, and temperature of each node. These data are transmitted and stored on a remote web server devoted to the automatic management of alarms and accessible for data consulting. The proposed system is currently operating in different experimental fields in Italy.

In this paper, the implementation of a low-voltage class AB second generation voltage conveyor (VCII) with high current drive capability is presented. Simple realization and good overall performance are the main features of the proposed circuit. Proper solutions and techniques were used to achieve high signal swing and high linearity at Y, X and Z ports of VCII as well as low-voltage operation. The operation of the proposed VCII was verified through SPICE simulations based on TSMC 0.18 mu m CMOS technology parameters and a supply voltage of +/- 0.9 V. The small signal impedance values were 973 Omega, 120 k Omega and 217 Omega at Y, X and Z ports, respectively. The maximum current at the X port was +/- 10 mA with maximum total harmonic distortion (THD) of 2.4% at a frequency of 1 MHz. Considering a bias current (I-B) of 29 mu A and output current at the X port (I-X) of 10 mA, the current drive capability (I-X/I-B) of about 345 was achieved at the X port. The voltage swing at the Z port was (-0.4, 0.4) V. The THD value at the Z port for an input signal with 0.8 V peak-to-peak value and frequency of 1 MHz was 3.9%. The total power consumption was 0.393 mu W. innovation project iRel4.0 ECSEL [876659] This research has been partially founded by the European co-funded innovation project iRel4.0 ECSEL under grant agreement No 876659.