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Unclamped Inductive Switching (UIS) is a very high stress test used for characterizing the ruggedness in terms of the maximum avalanche energy can be handled by the device. Optimizing the design for better reliability and ruggedness of power MOSFET was studied. In this paper, we investigated effects of current density and hotspot temperature distribution during unclamped inductive switching (UIS) test for P-channel LDMOSFET. It is shown that the simulation results are found to be in good correlation between the maximum avalanche energy handling capability and identification of the mechanism of device-failure (current density distribution effects and hotspot temperature location). Uniformity of current density in each finger of the device can help to improve the maximum avalanche energy handling capability. If current density distribution and temperature hotspot region effects can be suppressed more uniform in each finger of the critical regions, the device is expected to sustain higher avalanche energy during stress.

To increase typically low output drive currents from Si Nanowire field-effect transistors (FETs), we show a GaN based GAA Nanowire FET’s effectiveness. The theoretical study is focused on the three dimensional device designs, comparisons, random dopant fluctuation using IFM, and general variability issues including nanowire length, gate work function, and channel thickness are discussed. Performance of GaN GAA Nanowire is found to be increasing as Gate length is increased. Electrical characteristics of FETs including threshold voltage saturation, On/Off current ratio and sub threshold slope (SS) are analyzed. GaN GAA structure let to gate control ability improvement compared to Si based Nanowire in electrical performance. The GaN GAA Nanowire subthreshold slope is ~62mV/decade, which is close to the theoretical limit 60 mV/decade and leads to very high Ion/Ioff ratio of 1010-1011. The GaN GAA Nanowire is a very promising candidate for high-performance.

In this paper, a low-cost 900V rated multiple RESURF lateral double-diffused MOS (LDMOS) transistor in junction-isolated power IC technology without EPI layer is developed and successfully simulated. Don't think that the bigger the processing node the lower the cost. There are LDMOS processes today at the 0.35-micron node that use the same number of masks that are required at the 1.0-micron node. Moreover, smaller processing nodes yield smaller chip sizes, which carry both performance and cost benefits. Evaluate EPI vs. non-EPI wafers, and if your performance requirements can be met with non-EPI that is the best choice for lower cost implementation. Detailed device simulations and structure designs have been done. The optimized devices show excellent performance, which have been demonstrated with characterization results from device. The proposed multiple RESURF LDMOS without EPI Layer is able to achieve a specific on-resistance of lower than 250 mΩ-cm2 while maintaining a breakdown of over 900 volts.

In this paper, the effect of poly-gate extension on improved ruggedness of n-type LDMOS is evaluated by two-dimensional (2D) device and circuit simulation. Multi-finger dimension of n-type LDMOS is subjected to Unclamped Inductive Switching (UIS) stress test to determine its ruggedness. It is shown that the poly-gate extended device yields approximately 15% higher avalanche energy handling capability (Emax) as compared to that without extended poly-gate region. This work suggests that the improvement in ruggedness of the optimized design is attributed to the suppression and shift of the electric field peaks away from the critical regions. The results from simulation are found to be in good correlation with experimental UIS test results in terms of avalanche energy range, identification of the mechanism of device-failure and hot-spot location. It is believed from the results obtained that this approach will have remarkable impact in the ruggedness if implemented for large-array devices (LAD).

This work demonstrates the effect of increasing finger number and width on the ruggedness of the nLDMOS device under test (DUT). The ruggedness or energy handling capability is analyzed by two-dimensional (2-D) and three dimensional (3-D) device and circuit simulations. The set failure criterion in our study and simulation is the device temperature reaching a critical value equal to the melting point of metal-contacts. The maximum energy is calculated by considering the pass-case prior to device failure and time-integrating the drain voltage and current for the avalanche duration. Maximum avalanche energy handling capability is seen to be increased linearly with number of device fingers. UIS test was also performed on width extended multi-finger nLDMOS device structures. The simulated results provided useful approaches to predict real experimental results and contribute to their physical interpretation by identification of the mechanism of device-failure, hot-spot location and continuous temperature extraction.

The effect of negative, neutral and positive stress by Si3N4 film on AlGaN layer of AlGaN/GaN based high electron mobility transistor (HEMT) heterostructure has been investigated by varying different stress values using Synopsys Sentaurus device simulation. This paper shows a relation between the stresses of passivation layer, two dimensional electron gas (2DEG) formed at the interface of AlGaN/GaN region and respective drain current. The increase in negative stress will result in the increase of 2DEG density, which will result in the increase of drain current. Additionally, the 2DEG density was found to be depended on the applied bias voltage, showing the higher drain sweep voltage will increase the 2DEG density. This study also provides the effect of stress on direct-current (DC) capacitance-voltage characteristics of device electrical performance. It suggests that the capacitance will be increased with the increasing positive stress, indicating the change in interface states due to stress effect.

This paper reports a novel device structure which operates at low electrical field and high potential at internal drain point .The kink and quasi-saturation effects were minimized for this small 0.15 micron SOI LDNMOS with 0.13 micron gate length. Numerical simulation is used to show that the potential and electric field distribution within a small linear thickness (LT) LDMOS SOI device is quite different from that observed lateral linear doping (LD), uniform and vertical linear doping (VLD) devices. Reduction of drain electric field and of inter drain point potential barrier brings about a dramatic decrease of Kink effect improvement of quasi-saturation, large safe operate area (SOA) performance and lower on-resistance (Ron).

Lateral DMOS power devices can achieve high breakdown voltage by optimizing the two dimensional (2-D) device parameters in accordance with the RESURF principle. However, in practice, it is also necessary to optimize the three dimensional (3-D) device parameters in order to support a given breakdown voltage. In this paper, We report the effect of 3-D parameters such as the curvatures of the drain and source regions, doping density of LDMOS device with SOI (Silicon-On-Insulator) substrates based on numerical simulations and analytical solutions using cylindrical coordinates with device simulator "MEDICI" and Synopsys 3D simulator Sentaurus 2009.06-SP2 version. We stress the necessary 3D simulation for power device with racetrack, interdigitated layouts etc.

A variety of lateral high-voltage devices has been investigated in the range of 200V to 300V applications in power ICs, including reduced surface electric field (RESURF), laterally double diffused MOS (LDMOS) transistor, lateral variation doping (LVD), vertical linear doping (VD) and linear thickness (LT) devices. These devices are described and compared on the basis of on-state, off-state breakdown voltages, on-state resistance (Rdson), safe operation area (SOA) and Baliga's Figure-Of-Merits (BFOM). It is observed that for devices operating lesser than 300V, the VD LDMOS exhibits superior performance, where as higher voltage devices (≧300 V), the LT device proves to be superior. Applications arround 200 V, the VD device exhibits only a marginal improvement over the LT LDMOS device.

The high junction leakages, circuit latched issues, and high parasite capacitances happened in junction isolation technology can be improved by the thin SOI (Silicon-On-Insulator) technology. A CMOS compatible SOI technology will be one of technologies used in the future roadmap of LDMOS devices. A CMOS compatible thin SOI LDMOS (Lateral Double-diffused MOSFET) device, with 0.18 micron gate length, 0.02 micron gate oxide and 3 micron N-drift region, is proposed to achieve the optimal (BVoff) off-state breakdown voltage and on-state resistance (Ron) values. The characteristics of the proposed LDMOS device are verified by the two-dimensional process simulator TSuprem-IV and the device simulator Medici. The simulated results have shown that a device performance at the range of BVoff, 80 v, and Ron, 190 mohm-mm2, is attended. The on-state breakdown voltage is measured at 70V with an excellent safe operating area (SOA) performance for the drain source current versus on-state breakdown voltage.