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The silicon-based planar CMOS technology is expected to face fundamental limits in the near future, and therefore, new types of nanoscale devices are being investigated aggressively. To understand the device physics and assess their performance limits, new types of simulation techniques considering quantum mechanical phenomena, carrier's ballistic transport and atomistic effects are also needed. In this paper, we present our recent approaches toward the quantum and atomistic transport modeling, and make a performance projection of emerging nano-MOS transistors employing new device structures and new channel materials.

In this paper, we study the influences of channel source-end potential profile on ballistic transport of carriers in Si-MOSFETs based on a quantum-corrected Monte Carlo device simulation. As a result, we found that a higher ballistic efficiency is expected in MOSFETs with a heterojunction source-end barrier such as Schottky source/drain (S/D) MOSFETs, than that of the conventional PN junction S/D MOSFETs. Such a superior ballistic behavior is demonstrated due to the narrower bottleneck barrier profile formed at the source-channel interface.