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Three-dimensional stacked memory has attracted much attention due to its advantages such as high-speed operation, low-power consumption, and high-level integration. Many researchers have reported various novel approaches to achieve three dimensional device integration, including wafer bonding, epitaxial lateral overgrowth (ELO), zone melting recrystallization (ZMR), and lateral-solid phase epitaxy (L-SPE). These methods have some limitations, in terms of the requirement of stacked memory process which include simple integration process, low thermal budget due to the performance degradation of underlying devices and single crystalline quality on oxide. In this work, we suggest a laser-induced epitaxial growth (LEG) process that utilizes a single crystalline seed grown by selective epitaxial growth (SEG) process. This seed layer was formed in patterned contact holes linking the substrate Si and the stacked layer. A raised seed could prevent the degradation of electrical properties of underlying devices. An excimer laser was then used as a light source of the epitaxial growth via recrystallization to melt the deposited amorphous Si films both on oxide layer and seed contact during several nano-seconds.

In this study, SiBN films were prepared by plasma assisted atomic layer deposition (PAALD) using dichlorosilane, boron trichloride and ammonia as source gases. In this material system, the reaction control of boron, silicon and nitrogen is a key issue because nitrogen reacts more readily with boron than with silicon. On the other hand, ammonia radicals created by remote plasma during PAALD enhance the reaction between silicon and nitrogen. Therefore, PAALD enables an enhanced controllability of silicon and boron contents. SiBN films with dielectric constant of 4.45 to 5.47 were applied to buried- contact (BC) spacer instead of SiN films in 70 nm DRAM device, and 12 - 24% reduction of bit-line loading capacitance (CBL) was obtained. Low-k SiBN films using PAALD are promising materials for insulating interlayer such as Si3N4 spacer for future sub-70 nm DRAM devices.