Search

To establish elemental technologies of thick 4H-SiC epitaxial growth for very high voltage bipolar devices, reduction methods for Z1/2 center, BPDs and in-grown stacking faults have been investigated. Complete elimination of the Z1/2 center in a very thick (>100 μm) epilayer and significant enhancement of carrier lifetimes are achieved by growing the epilayer under proper conditions followed by application of the post-growth process. A new method to convert remaining BPDs in an epilayer to TEDs by simple high temperature annealing is demonstrated. We also discuss the growth conditions to minimize the formation of the in-grown stacking faults during epitaxial growth under a H2+SiH4+C3H8 system.