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Resistive random access memory (ReRAM), or memristors, may be capable of significantly improving the efficiency of neuromorphic computing, when used as a central component of an analog hardware accelerator. However, the significant electrical variation within a single device and between devices degrades the maximum efficiency and accuracy which can be achieved by a ReRAM-based neuromorphic accelerator. In this report, the electrical variability is characterized, with a particular focus on that which is due to fundamental, intrinsic factors. Analytical and ab initio models are presented which offer insight into the factors responsible for this variability.

In this work, we have characterized a variety of SiC devices (first- and second-generation 1200 V SiC MOSFETs and 1200 V SiC JFETs) with regards to threshold voltage shifts and leakage currents at high temperatures under both static and dynamic gate bias stress conditions. It was found that, although the stability of SiC MOSFETs has increased dramatically from the first- to the second-generation due to an increase in the quality of the gate oxide layer, SiC JFET devices (which lack a gate oxide altogether) are much more stable with respect to DVT for both types of gate bias stresses at high temperatures. We have also characterized the interface trap density (DIT) in SiC MOSFETs based solely on changes in the sub-threshold slope of the devices' I-V curves under elevated temperature and bias stress, and have produced [?]DIT profiles showing relative changes in interfacial defect concentration at energy levels referenced to the calculated surface potential at the threshold voltage. We have found that the defect density of second-generation SiC MOSFETs is almost an order of magnitude lower than similar first-generation devices from the same manufacturer, consistent with the decreased VT shifts seen in voltage/temperature stress experiments.

Bias-temperature stress experiments performed on two generations of SiC power MOSFETs from the same manufacturer show reductions in threshold voltage (VT) shift at elevated temperatures from first- to second-generation. The negative VT shift is reduced from a range of -1 V to -1.6 V to a range of -100 mV to -300 mV for temperatures from 125degC to 175degC. Plastic-packaged parts show a gate-bias-independent junction leakage current at temperatures above the rated temperature, suggesting that the plastic packaging introduces an extrinsic leakage path. Junction leakage in metal-packaged parts can be significantly reduced by applying a small negative gate bias at elevated temperatures. Switching gate bias temperature stresses show VT shifts dependent on duty cycle, with a higher duty cycle resulting in a higher rate of VT shift. Cumulative damage effects may be observed between switching gate bias stresses.

Resistive random access memory (ReRAM), or memristors, may be capable of significantly improving the efficiency of neuromorphic computing, when used as a central component of an analog hardware accelerator. However, the significant electrical variation within a single device and between devices degrades the maximum efficiency and accuracy which can be achieved by a ReRAM-based neuromorphic accelerator. In this report, the electrical variability is characterized, with a particular focus on that which is due to fundamental, intrinsic factors. Analytical and ab initio models are presented which offer insight into the factors responsible for this variability.